Abstract
Nowadays, due to the high capabilities of nanotechnology in designing multi-valued logic (MVL) circuits, much research has been done to design MVL circuits in nanotechnology. The use of MVL circuits reduces chip interconnections, thereby decreasing the chip area and power consumption. Various methods have been proposed to produce logic ‘1’ in the ternary logic circuits; these include the use of voltage division on VDD and application of two supply voltages. The use of two supply voltages increases the interconnections, which is against one of the multi-valued logic aims, and using voltage division on VDD can cause considerable static power dissipation. In this paper, based on the multi-threshold voltage of CNFET, the circuits are designed to charge a load capacitor to VDD/2 or discharge to VDD/2 in order to produce logic ‘1’ by a novel structure of diode-connected transistors. Thus, with the use of the single-supply voltage, the direct current is eliminated and the static power consumption is dropped sharply. As expected, the simulation results show that the proposed designs have considerably low power consumption with the same delay; thus, they offer a considerably lower PDP in comparison with other single-supply designs with the same noise margin.
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The datasets generated during the current study are available from the corresponding author on reasonable request.
References
M. Bagherizadeh, M. Eshghi, Two novel low-power and high-speed dynamic carbon nanotube full-adder cells. Nanoscale Res. Lett. 6, 519 (2011)
A. Daraei, S.A. Hosseini, Novel energy-efficient and high-noise margin quaternary circuits in nanoelectronics. AEU Int. J. Electron. Commun. 105, 145–162 (2019)
A.P. Dhande, V.T. Ingole, V.R. Ghiye, Ternary Digital System: Concepts and Applications. SM Medical Technologies Private Limited. (2014)
S. Etezadi, S.A. Hosseini, Novel ternary logic gates design in nanoelectronics. Adv. Electr. Electron. Eng. (2019). https://doi.org/10.15598/aeee.v17i3.3156
A. Ghadiyani, A. Shahhoseini. A new ternary memory cell based on CNFETs using forced stack technique, in 3rd International Conference on Electrical Engineering (2018)
M. Ghelichkhan, S.A. Hosseini, S.H. Pishgar Komleh, Multi-digit binary-to-quaternary and quaternary-to-binary converters and their applications in nanoelectronics. Circuits Syst. Signal Process. 39, 1920–1942 (2019)
A. Heung, H.T. Mouftah, Depletion/enhancement CMOS for a low power family of three-valued logic circuits. IEEE J. Solid-State Circuits 20, 609–616 (1985)
S.A. Hosseini, E. Roosta, A novel low complexity and energy-efficient method to implement quaternary logic function in nanoelectronics. Circuits Syst. Signal Process. 102, 104821 (2020)
S.A. Hosseini, S. Etezadi, Novel low storage power and high noise margin ternary memory cell in nanoelectronics. IET Circuits Dev. Syst. 24, 1751–8598 (2020)
S.A. Hosseini, S. Etezadi, A novel very low-complexity multi-valued logic comparator in nanoelectronics. Circuits Syst. Signal Process. 39, 223–244 (2020)
J. Huang, M. Zhu, P. Guptay, Sh. Yang, S.M. Rubinz, G. Garretz, J. He. A CAD Tool for design and analysis of CNFET circuits, in IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC). pp. 1–4 (2010)
M.R. Khezeli, M.H. Moaiyeri, A. Jalali, Active shielding of MWCNT bundle interconnects: an efficient approach to cancellation of crosstalk-induced functional failures in ternary logic. IEEE Trans. Electromagn. Compat. (2018). https://doi.org/10.1109/temc.2017.2788500
M.R. Khezeli, M.H. Moaiyeri, A. Jalali, Comparative analysis of imultaneous switching noise effects in MWCNT bundle and Cu power interconnects in CNFET-based ternary circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27, 37–46 (2019)
Y. Lin, J. Appenzeller, J. Knoch, P. Avouris, High-performance carbon nanotube field-effect transistor with tunable polarities. IEEE Trans. Nanotechnol. 4, 481–489 (2005)
S. Lin, Y. Kim, F. Lombardi, CNFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. 10, 217–225 (2011)
M.S. Mastoori, F. Razaghian, A novel energy-efficient ternary successor and predecessor using CNTFET. Circuits Syst. Signal Process. 35, 875–895 (2016)
R.F. Mirzaee et al., Differential cascode voltage switch (DCVS) strategies by CNFET technology for standard ternary logic. Microelectron. J. 44, 1238 (2013)
M.H. Moaiyeri et al., A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits. IET Comput. Digital Tech. 7, 167–181 (2013)
M.H. Moaiyeri et al., Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circuits Dev. Syst. 5, 285–296 (2011)
M.H. Moaiyeri, R. Mirzaee, K. Navi, A. Momeni, Design and analysis of a high-performance CNFET-based Full Adder. Int. J. Electron. 99, 113–130 (2012)
M.H. Moaiyeri, Z. Hajmohammadi, M.R. Khezeli, A. Jalali, Effective reduction in crosstalk effects in quaternary integrated circuits using mixed carbon nanotube bundle interconnects. ECS J. Solid State Sci. Technol. 7, 69–76 (2018)
M.H. Moaiyeri, Z.M. Taheri, M.R. Khezeli, A. Jalali, Efficient passive shielding of MWCNT interconnects to reduce crosstalk effects in multiple-valued logic circuits. IEEE Trans. Electromag. Comp. (2018). https://doi.org/10.1109/temc.2018.2863378
K. Rahbari, S.A. Hosseini, Novel ternary D-Flip-Flap-Flop and counter based on successor and predecessor in nanotechnology. AEU Int. J. Electron. Commun. 109, 107–120 (2019)
A. Raychowdhury, K. Roy, Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Trans. Nanotechnol. 4, 168–179 (2005)
E. Roosta, S.A. Hosseini, A novel multiplexer-based quaternary full adder in nanoelectronics. Circuits Syst. Signal Process. 38, 4056–4078 (2019)
M. Shahangian, S. A Hosseini, R.Faghih Mirzaee, A universal method for designing multi-digit ternary-to-binary converter using CNTFET. J. Circuits, Syst. Comput. 1793–6454 (2019)
M. Shahangian, S.A. Hosseini, S.H. PishgarKomleh, Design of a multi-digit binary-to-ternary converter based on CNTFETs. Circuits Syst. Signal Process. 38, 2544–2563 (2019)
E. Shahrom, S.A. Hosseini, A new low power multiplexer based ternary multiplier using CNTFETs. Int. J. Electron. Commun. (AEÜ) 93, 191–207 (2018)
A. Singh, M. Khosla, B. Raj, Design and analysis of electrostatic doped Schottky barrier CNFET based low power SRAM. AEU: Int. J. Electron. Commun. 80, 67–72 (2017)
K. Sridharan, S. Gurindagunta, V. Pudi, Efficient multiternary digit adder design in CNFET technology. IEEE Trans. Nanotechnol. 12, 283–287 (2013)
Stanford University CNFET model Website. Stanford University, Stanford, CA [Online]. Available: http://nano.stanford.edu/model.php?id=23 (2008)
S. Tabrizchi, F. Sharifi, Z.M. Saifulla, A.H. Badawy. Enabling Energy-Efficient Ternary Logic Gates using CNFETs, in 17th IEEE International Conference on Nanotechnology (2017)
S. Tabrizchi, M.R. Taheri, K. Navi, N. Bagherzadeh, Novel CNFET ternary circuit techniques for high-performance and energy efficient design. IET Circuits Devices Syst. 2, 193–202 (2019)
M. Takbiri et al., Analytical review of noise margin in MVL, Clarification of a deceptive matter. Circuits Syst. Signal Process. 38, 4280 (2019)
C. Vudadha, S.P. Parlapalli, M.B. Srinivas, Energy efficient design of CNFET-based multi-digit ternary adders. Microelectron. J. 75, 75–86 (2018)
N.H.E. Weste, D.M. Harris, CMOS VLSI design a circuits and systems perspective (Addison-Wesley, Boston, 2009)
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Hosseini, S.A., Roosta, E. A Novel Technique to Produce Logic ‘1’ in Multi-threshold Ternary Circuits Design. Circuits Syst Signal Process 40, 1152–1165 (2021). https://doi.org/10.1007/s00034-020-01535-2
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DOI: https://doi.org/10.1007/s00034-020-01535-2