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Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique

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Abstract

For computational arithmetic, a full adder is the primary logic units in VLSI applications. A new full adder circuit design has been presented in this article which is based on input switching activity pattern and gate diffusion input (GDI) technique. The adder has been designed in two stages. The first stage is an XOR–XNOR module, whereas, the final stage is for the required outputs. By using the switching activity pattern of inputs and GDI techniques at each stage, the switching activities of the transistors have been minimized. This improves delay, power consumption and computational complexity. The adder has been designed and evaluated by using the synopsis tool and compared with different existing adder cells found in the literature. It is found that the presented adder shows an improvement at least 72.86% and 66.67% in terms of speed and energy consumption, respectively. Extensive performance analyses of the full adder have also been evaluated at 32 nm CMOS and 32 nm CNFET technology node which shows promising performances in both the technology nodes.

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References

  1. S. Abbasalizadeh, B. Forouzandeh, Full adder design with GDI cell and independent double gate transistor, in 20th Iranian Conference on Electrical Engineering (ICEE2012) (Tehran 2012), pp. 130–134

  2. S. Abed, Y. Khalil, M. Modhaffar, I. Ahmad, High-performance low-power approximate Wallace tree multiplier. Int. J. Circ. Theor. Appl. 46, 2334–2348 (2018)

    Article  Google Scholar 

  3. A.K. Agrawal, S. Wairya, R.K. Nagaria, A new mixed gate diffusion input full adder topology for high speed low power digital circuits. World Appl. Sci. J. 7, 138–144 (2009)

    Google Scholar 

  4. M. Aguirre-Hernandez, M. Linares-Aranda CMOS full-adders for energy-efficient arithmetic applications. IEEE Trans. Very Large Scale Integr. Syst. 19(4), 718–721 (2011)

  5. M. Amini-Valashani, M. Ayat, S. Mirzakuchaki, Design and analysis of a novel low-power and energy-efficient 18 T hybrid full adder. Microelectron. J. 74, 49–59 (2018)

    Article  Google Scholar 

  6. M. Anis, M. Allam, M. Elmasry, Impact of technology scaling on CMOS logic styles. IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process. 49, 577–588 (2002)

    Article  Google Scholar 

  7. G. Balamurugan, N.R. Shanbhag, The twin-transistor noise-tolerant dynamic circuit technique. IEEE J. Solid-State Circuits 36(2), 273–280 (2001)

    Article  Google Scholar 

  8. P. Battacharyya, B. Kundu, S. Ghosh, V. Kumar, A. Dandapat, Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23(10), 2001–2008 (2015)

  9. H.T. Bui, Y. Wang, Y. Jiang, Design and analysis of low-power 10-transistor full adders using novel XOR–XNOR gates. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 49(1), 25–30 (2002)

    Article  Google Scholar 

  10. K.K. Chaddha, R. Chandel, Design and analysis of a modified low power CMOS full adder using gate-diffusion input technique. J. Low Power Electron. 6(4), 482–490 (2010)

    Article  Google Scholar 

  11. H. Chang, J. Gu, M. Zhang, A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits. IEEE Trans. Very Large Scale Integr. Syst. 13(6), 686–695 (2005)

    Article  Google Scholar 

  12. R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros et al., Benchmarking nanotechnology for high-performance and low-power logic transistor applications. IEEE Trans. Nanotechnol. 4, 153–158 (2005)

    Article  Google Scholar 

  13. J. Deng, H.S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part II: full device model and circuit performance benchmarking. IEEE Trans. Electron Dev. 54(12), 3195–3205 (2007)

    Article  Google Scholar 

  14. J. Deng, H.S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part I: model of the intrinsic channel region. IEEE Trans. Electron Dev. 54(12), 3186–3194 (2007)

    Article  Google Scholar 

  15. V. Foroutan, M. Taheri, K. Navi, A.A. Mazreah, Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style. Integr. VLSI J. 47(1), 48–61 (2013)

    Article  Google Scholar 

  16. F. Frustaci, P. Corsonello, S. Perri, G. Cocorullo, High-performance noise-tolerant circuit techniques for CMOS dynamic logic. IET Circuits Dev. Syst. 2(6), 537–548 (2008)

    Article  Google Scholar 

  17. S. Goel, A. Kumar, M.A. Bayoumi, Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style. IEEE Trans. Very Large Scale Integr. Syst. 14(12), 1309–1321 (2006)

    Article  Google Scholar 

  18. M. Hasan, M.J. Hossein, M. Hossain, H.U. Zaman, S. Islam, Design of a scalable low-power 1-bit hybrid full adder for fast computation. IEEE Trans. Circuits Syst. II Express Briefs (2019). https://doi.org/10.1109/TCSII.2019.2940558

  19. I. Hassoune, D. Flandre, I. O’Connor, J. Legat, ULPFA, A new efficient design of a power-aware full adder. IEEE Trans. Circuits Syst. I Reg. Pap. 57(8), 2066–2074 (2010)

    Article  MathSciNet  Google Scholar 

  20. I. Hussain, S. Chaudhury, A comparative study on the effects of technology nodes and logic styles for low power high-speed VLSI applications. Int. J. Nanoparticles 12(1/2), 122 (2020)

    Article  Google Scholar 

  21. I. Hussain, M. Kumar, Design and performance analysis of a 3–2 compressor by using improved architecture. J. Active Passive Electron. Dev. 12(3–4), 173–181 (2017)

    Google Scholar 

  22. I. Hussain, M. Kumar, A fast and reduced complexity wallace multiplier. J. Active Passive Electron. Dev. 12(1–2), 63–71 (2017)

    Google Scholar 

  23. I. Hussain, A. Singh, S. Chaudhury, A review on the effects of technology on CMOS and CPL logic style on performance, speed and power dissipation, in 2018 IEEE Electron Devices Kolkata Conference (EDKCON) (Kolkata, India, 2018), pp. 332–336

  24. I. Hussain, C.K. Pandey S. Chaudhury, Design and analysis of high performance multiplier circuit, in 2019 Devices for Integrated Circuit (DevIC) (Kalyani, India, 2019), pp. 245–247

  25. I. Hussain, S. Chaudhury, A new 4–2 compressor for VLSI circuits and systems, in Advances in Smart System Technologies. Advances in Intelligent Systems and Computing, eds. by P. Suresh, U. Saravanakumar, M. Hussein Al Salameh, vol. 1163 (Springer, Singapore, 2020)

  26. I. Hussain, S. Chaudhury, CNFET based low power full adder circuit for VLSI applications. Nanosci. Nanotechnol. (2020). https://doi.org/10.2174/2210681209666190220122553

  27. I. Hussain, S. Chaudhury, Performance comparison of 1-bit conventional and hybrid full adder circuits, in Advances in Communication, Devices and Networking. Lecture Notes in Electrical Engineering, eds. by R. Bera, S. Sarkar, S. Chakraborty, vol. 462 (Springer, Singapore, 2018)

  28. J.J. Kim, K. Roy, Double gate-MOSFET sub-threshold circuit for ultralow power applications. IEEE Trans. Electron. Dev. 51, 1468–1470 (2004)

    Article  Google Scholar 

  29. P. Kumar, R.K. Sharma, An energy efficient logic approach to implement CMOS full adder. J. Circuits Syst. Comput. 26(5), 1–20 (2017)

    Article  Google Scholar 

  30. M. Kumar, J.S. Ubhi, Design and analysis of CNFET based 10 T SRAM for high performance at nanoscale. Int. J. Circ. Theor. Appl. (2019). https://doi.org/10.1002/cta.2696

    Article  Google Scholar 

  31. R. Lorenzo, S. Chaudhury, Dynamic threshold sleep transistor technique for high speed and low leakage in CMOS circuits. Circuit Syst. Signal Process. 36(7), 2654–2671 (2016)

    Article  Google Scholar 

  32. A.T. Mahani, P. Keshavarzian, A novel energy-efficient and high speed full adder using CNFET. Microelectron. J. 61, 79–88 (2017)

    Article  Google Scholar 

  33. Y.S. Mehrabani, M. Eshghi, High-speed, high-frequency and low-PDP, CNFET full adder cells. J. Circuits Syst. Comput. 24(09), 1550130 (2015)

    Article  Google Scholar 

  34. M.H. Moaiyeri, R.F. Mirzaee K. Navi, et al., Efficient CNFET-based ternary full adder cells for nanoelectronics. Nano-Micro Lett. 3, 43 (2011)

  35. A. Morgenshtein, A. Fish, I.A. Wagner, Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits. IEEE Trans. Very Large Scale Integr. Syst. 10(5), 566–581 (2002)

    Article  Google Scholar 

  36. A. Morgenshtein, M. Moreinis, R. Ginosar, Asynchronous gate-diffusion-input (GDI) circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(8), 847–856 (2004)

    Article  Google Scholar 

  37. H. Naseri, S. Timarchi, Low-power and fast full adder by exploring new XOR and XNOR gates. IEEE Trans. Very Large Scale Integr. Syst. 26(8), 1481–1493 (2018)

    Article  Google Scholar 

  38. K. Navi, A. Momeni, F. Sharifi, P. Keshavarzian, Two novel ultra high speed carbon nanotube full-adder cells’. IEICE Electron. Express 6(19), 1395–1401 (2009)

    Article  Google Scholar 

  39. P. Ng, P.T. Balsara, D. Steiss, Performance of CMOS differential circuits. IEEE J. Solid-State Circuits 31, 841–846 (1996)

    Article  Google Scholar 

  40. M.C. Parameshwara, H.C. Srinivasaiah, Low-power hybrid 1-bit full adder circuit for energy efficient arithmetic applications. J. Circuits Syst. Comput. 26(1), 1–15 (2017)

    Article  Google Scholar 

  41. S. Perri, M. Lanuzza, P. Corsonello, Design of high-speed low-power parallel-prefix adder trees in nanometer technologies. Int. J. Circ. Theor. Appl. 42, 731–743 (2014)

    Article  Google Scholar 

  42. J.M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd edn. (Pearson Education, Delhi, 2003)

    Google Scholar 

  43. Radhakrishnan, Low-voltage low-power CMOS full adder, in IEE Proceedings—Circuits, Devices and Systems (2001). https://doi.org/10.1049/ip-cds:20010170

  44. R. Shanmuganathan, K. Brindhadevi, Comparative analysis of various types of multipliers for effective low power. Microelectron. Eng. 214, 28–37 (2019)

    Article  Google Scholar 

  45. Stanford University, Stanford CNFET Model—HSPICE. https://nano.stanford.edu/stanford-cnfet-model. Accessed on August 2017 (2017)

  46. R. Vaddi, S. Dasgupta, R.P. Agarwal, Device and circuit co-design robustness studies in the sub-threshold logic for ultralow-power applications for 32 nm CMOS. IEEE Trans. Electron. Dev. 57, 654–664 (2010)

    Article  Google Scholar 

  47. M. Vesterbacka, A 14-transistor CMOS full adder with full voltage-swing nodes, in 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No. 99TH8461) (Taipei, Taiwan, 1999), pp. 713–722

  48. S. Wairya, R.K. Nagaria, S. Tiwari, New design methodologies for high-speed low-voltage 1 bit CMOS full adder circuits. Int. J. Comput. Technol. Appl. 2(2), 190–198 (2011)

    Google Scholar 

  49. J.-M. Wang, S.-C. Fang, W.-S. Feng, New efficient designs for XOR and XNOR functions on the transistor level. IEEE J. Solid-State Circuits 29, 780–786 (1994)

    Article  Google Scholar 

  50. I. Wegener, The Complexity of Boolean Functions (Wiley and B. G. Teubner, London, 1987)

  51. M. Zhang, J. Gu, C.-H. Chang, A novel hybrid pass logic with static CMOS output drive full-adder cell, in Proceedings of the 2003 International Symposium on Circuits and Systems (Bangkok, Thailand, 2003), pp. 317–320

  52. N. Zhu, W.L. Goh, W. Zhang, K.S. Yeo, Z.H. Kong, Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing. IEEE Trans. Very Large Scale Integr. Syst. 18(8), 1225–1229 (2010)

  53. R. Zimmermann, Binary adder architectures for cell-based VLSI and their synthesis. PhD. thesis, Dipl. Informatik-Ing. ETH (1996)

  54. R. Zimmermann, W. Fichtner, Low-power logic styles: CMOS versus pass-transistor logic. IEEE J. Solid-State Circuits (1997). https://doi.org/10.1109/4.597298

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Acknowledgements

The authors would like to thank MHRD (MoE), India for providing the fellowship.

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  1. Department of Electrical Engineering, National Institute of Technology Silchar, Silchar, India

    Inamul Hussain & Saurabh Chaudhury

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Hussain, I., Chaudhury, S. Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique. Circuits Syst Signal Process 40, 1762–1787 (2021). https://doi.org/10.1007/s00034-020-01550-3

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