Abstract
High-speed video coding and compression are extensively used in many IoT applications with optimum data usage and resolution using three-dimensional discrete cosine transforms (3D-DCT). We propose an efficient hardware implementation for high-speed vector-radix decimation-in-frequency (VR-DIF) 3D-DCT with an optimum area and power consumption. In the previous implementation, the data path arithmetic units used a fixed word length (either 16 or 18 or 21 bits), whereas the proposed architecture uses the range of word length from 11 bits (1-bit sign, 1-bit integer and 9-bit fraction) to 20 bits (1-bit sign, 10-bit integer and 9-bit fraction) to achieve lower silicon area and power consumption. The architecture is optimally pipelined to achieve high processing speed (above 3 Giga samples/s). To test the proposed architecture, an \(8\times 8\times 8\) video cube with a pixel depth of 8 bits is considered. The arithmetic functional units such as signed adder/subtractor and cosine coefficient multipliers required for implementing \(8\times 8\times 8\) 3D-DCT/IDCT processor is designed with the proposed variable word length. The core of VR-DIF 3D-DCT/IDCT with the variable word length is implemented using TSMC 90 nm technology library. The proposed architecture consumes 26.5% and 23.2% lesser area and power, respectively, than the existing fixed word length 3D-DCT-II implementation tested with a maximum frequency of 653 MHz.
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Acknowledgements
This research was financially supported by The Research Start-Up Fund Subsidized Project of Shantou University, China, Grant No. NTF17016. The authors would like to thank CH Vijendra Kumar, M.Tech., VLSI design student for assisting in ASIC synthesis trails and Vellore Institute of Technology, Vellore, for providing laboratory facilities.
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Appendix
Appendix
The optimum word lengths for various stages of the architecture is analysed using the MATLAB model of VR-DIF 3D-DCT and VR-DIF 3D-IDCT and listed in the following Tables 7 and 8.
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Arunachalam, V., Joseph Raj, A.N. & Deepika, S. Performance Improvement of Vector-Radix Decimation-in-Frequency 3D-DCT/IDCT Using Variable Word Length. Circuits Syst Signal Process 40, 1818–1831 (2021). https://doi.org/10.1007/s00034-020-01557-w
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DOI: https://doi.org/10.1007/s00034-020-01557-w