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A Low Error, Hardware Efficient Logarithmic Multiplier

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Abstract

The ever-increasing requirement for high-performance signal processing blocks in artificial intelligence, IoT, and neural networks has rendered the Logarithmic arithmetic as front runner of advanced processors. As they require complex mathematical operations such as multiplication and division but they can be quickly done in the logarithmic domain as they are reduced to addition and subtraction operations, respectively. The task, though, is to move from binary to logarithmic and vice versa. Several algorithms have been suggested for the logarithmic and antilogarithmic conversion, but there is a compromise between hardware difficulty and accuracy. Within this work, we are introducing the correction circuit for both logarithmic and antilogarithmic conversion that is based on Mitchell’s algorithm. Here the correction terms are generated using a weighted average approach and are stored using 16 X 8 ROM. The terms for correction are selected using the characteristic of the logarithmic value. Then, these converters are used to design a logarithmic multiplier. To further simplify the multiplier, an optimized multiplier is proposed. It involves only the addition of a single term to the result before performing an antilogarithm operation, which also streamlined the application of the multiplier. The proposed multiplier and optimized multiplier involves only a memory unit and an adder apart from Mitchell’s logarithmic multiplier, so the hardware metrics are closely similar to Mitchell’s logarithmic multiplier while having a peak error rate of 9.4 \(\%\) and 7.5 \(\%\) which is 11.1 \(\%\) for Mitchell’s multiplier and has nearly 95\(\%\) of input combinations have less than 5\(\%\) error when multiplication is performed using proposed multipliers.

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Data sharing not applicable to this article as no datasets were generated or analysed during the current study

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Authors and Affiliations

  1. Department of ECE, GVP College of Engineering (A), Visakhapatnam, India

    L. Guna Sekhar Sai Harsha & Bhaskara Rao Jammu

  2. Department of ECE, JNTUK UCEV, Vizianagaram, India

    Nalini Bodasingi

  3. Department of ECE, GRIET, Hyderabad, India

    Sreehari Veeramachaneni

  4. Department of CSE, IITDM Kancheerpuram, Chennai, India

    Noor Mohammad SK

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  1. L. Guna Sekhar Sai Harsha
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Correspondence to Bhaskara Rao Jammu.

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Harsha, L.G.S.S., Jammu, B.R., Bodasingi, N. et al. A Low Error, Hardware Efficient Logarithmic Multiplier. Circuits Syst Signal Process 41, 485–513 (2022). https://doi.org/10.1007/s00034-021-01793-8

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