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An Optimization Methodology for Designing Hardware-Based Function Evaluation Modules with Reduced Complexity

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Abstract

The evaluation of mathematical functions is a critical task in several hardware designs, and piecewise polynomial approximation (PPA) is one of the main techniques widely used for function evaluation. This technique employs uniform and non-uniform segmentation for splitting the function and approaching each function segment via polynomial approximation, where lookup tables are needed to store the polynomial coefficients. Today, several hardware-based PPA implementations have address decoder units with a considerable amount of hardware complexity. To face this problem, this paper proposes a new methodology that searches the optimal function segments, polynomial coefficients, and their representation in fixed-point format when the design is constrained to a decoder word-length. Thus, a second-order PPA evaluation architecture based on the Horner’s rule and a simplified address decoder unit with reduced complexity are provided. The proposed methodology uses non-uniform segmentation relying on a linear combination of power-of-two, which results in a reduction of the number of segments and consequently in the hardware complexity of the address decoder unit. The figures of merit employed by the auto-tuning (self-adapting) segmentation process are the first-order derivative (slope) of the function and the signal to quantization noise ratio quality signal metric. Experimental results show a hardware reduction of the decoder design (number of segments, polynomial coefficient ROMs) when is compared with state-of-the-art proposals.

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Acknowledgements

The support of the Instituto Tecnológico de Sonora through PROFAPI Project Number 2021_0092 is gratefully acknowledged.

Author information

Authors and Affiliations

  1. Electronics and Electrical Engineering Department, Instituto Tecnológico de Sonora, Cd. Obregón, Sonora, Mexico

    G. González-Díaz-Conti & E. Ruiz-Ibarra

  2. Department of Electronics, Systems and IT, Western Institute of Technology and Higher Education, Tlaquepaque, Mexico

    O. Longoria-Gandara

  3. Department of Electronics, University of Guadalajara, Guadalajara, Mexico

    R. Carrasco-Alvarez

  4. Department of Mechatronics, Autonomous University of Yucatán, Mérida, Mexico

    A. Castillo-Atoche

  5. Department of Electrical Engineering, University of Quintana Roo, Chetumal, Mexico

    Javier Vázquez-Castillo

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  1. G. González-Díaz-Conti
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  4. E. Ruiz-Ibarra
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  6. Javier Vázquez-Castillo
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Correspondence to Javier Vázquez-Castillo.

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González-Díaz-Conti, G., Longoria-Gandara, O., Carrasco-Alvarez, R. et al. An Optimization Methodology for Designing Hardware-Based Function Evaluation Modules with Reduced Complexity. Circuits Syst Signal Process 41, 1530–1549 (2022). https://doi.org/10.1007/s00034-021-01835-1

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