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An Efficient VLSI Architecture for Fast Motion Estimation Exploiting Zero Motion Prejudgment Technique and a New Quadrant-Based Search Algorithm in HEVC

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A Correction to this article was published on 23 October 2021

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Abstract

In this manuscript, new quadrant-based search algorithm with zero motion prejudgment is proposed for motion estimation (ME) in HEVC (High Efficiency Video Coding) standard. The HEVC standard is used to obtain efficient output with low motion estimation time. The proposed quadrant-based search algorithm is a fast block matching algorithm that obtain better block matching amid the current block and reference block. The zero motion prejudgment (ZMP) method is used to find the block, whether it is motion or static and it is used for decreasing the computational complexity (CC) in the proposed quadrant-based search algorithm. The proposed quadrant-based search algorithm with ZMP technique for motion estimation in HEVC is implemented on the FPGA hardware platform. The entire architecture is executed in Verilog HDL with Virtex-5 technology and integrated with Xilinx ISE Design Suite 14.5. The results are integrated into the CIF (352 × 288 pixels) and HD (1280 × 720 pixels) video input sequence. The evaluation metrics like PSNR, Motion estimation time, sum of absolute difference (SAD) value are analyzed with existing method like hexagon, adaptive root pattern algorithm, and diamond search algorithm. Then the hardware parameters like power consumption and maximum operating frequency are measured. The hardware utilization is reduced and the power consumption of the proposed model is diminished to 0.143 W. The maximal operating frequency of the proposed model is 440.470 MHz. The experimental outcomes demonstrate that the proposed motion evaluation approach in HEVC is more effective than existing algorithms.

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Data Availability Statement

Data sharing not applicable to this article as no datasets were generated or analyzed during the current study.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Anna University, Chennai, India

    Francis H. Shajin

  2. Department of Electrical and Electronics Engineering, Anna University, Chennai, India

    P. Rajesh

  3. Department of Electrical Engineering, King Khalid University, Abha, Saudi Arabia

    M. Ramkumar Raja

Authors
  1. Francis H. Shajin
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  2. P. Rajesh
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  3. M. Ramkumar Raja
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Correspondence to Francis H. Shajin.

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The original online version of this article was revised: The given and the family name of the corresponding author was incorrectly structured. The author name was published as ‘Shajin H. Francis’ and the corrected name is ‘Francis H. Shajin’.

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Shajin, F.H., Rajesh, P. & Raja, M.R. An Efficient VLSI Architecture for Fast Motion Estimation Exploiting Zero Motion Prejudgment Technique and a New Quadrant-Based Search Algorithm in HEVC. Circuits Syst Signal Process 41, 1751–1774 (2022). https://doi.org/10.1007/s00034-021-01850-2

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