Abstract
Level shifters are the prominent interfacing circuits used in VLSI systems involving multiple supply voltages for their energy-efficient operation. The hybrid pull-up network (HPN)-based level shifter (HPLS) with an enhanced speed and energy performance is proposed in this paper that minimizes the voltage drop and current contention issue prevalent in the prior art. The HPN comprises the cross-coupled PMOS and the current mirror structure to improve the standby power performance. The proposed HPLS utilizes a split-input driver as an output stage to achieve both the area and energy efficiency. In addition, the usage of a pass transistor in the pull-down network enhances the speed performance by decreasing the rise/fall times. The performance of HPLS is verified by implementing it in CMOS 180 nm technology using Cadence tool and simulated through Spectre circuit simulator. The simulation results of the HPLS reveal 9.6 ns of delay and 66.77 fJ of energy consumption for the applied input signal of 0.4 V/1 MHz with 1.8 V high supply voltage. Further, it consumes smaller static power of 0.82 nW and occupies silicon area of 204 \(\upmu \)m\(^{2}\) (12 \(\upmu \)m \(\times \) 17 \(\upmu \)m).
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References
M. Alioto, Ultra-low power VLSI circuit design demystified and explained: a tutorial. IEEE Trans. Circuits Syst. I Reg. Pap. 59(1), 3–29 (2012)
T.H. Chen et al., Sub-threshold to above threshold level shifter design. J. Low Power Electron. 2(2), 251–258 (2006)
S.R. Hosseini et al., A low-power subthreshold to above threshold voltage level shifter. IEEE Trans. Circuits Syst. II Express Briefs 61(10), 753–757 (2014)
S.M. Kang et al., CMOS Digital Integrated Circuits: Analysis and Design, 4th edn. (Tata McGraw-Hill Education, New Delhi, 2009), pp. 721–724
Y. Kim, Y. Lee, D. Sylvester, D. Blaauw, SLC: Split-control level converter for dense and stable wide range voltage conversion, in Proceedings of the ESSCIRC (ESSCIRC) (2012), pp. 478–481
S. Kabirpour, M. Jalali, A power-delay and area efficient voltage level shifter based on a reflected-output Wilson current mirror level shifter. IEEE Trans. Circuits Syst. II Express Briefs 67(2), 250–254 (2020)
M. Lanuzza, P. Corsonello, S. Perri, Fast and wide range voltage conversion in multisupply voltage designs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23, 388–391 (2015)
S. Lutkemeier, U. Ruckert, A subthreshold to above-threshold level shifter comprising a Wilson current mirror. IEEE Trans. Circuits Syst. II Express Briefs 57(9), 721–724 (2010)
R. Lotfi et al., Energy-efficient wide-range voltage level shifters reaching 4.2 fJ/transition. IEEE J. Solid-State Circuits 1(2), 34–37 (2018)
V.L. Le, T.T.-H. Kim, An area and energy efficient ultra-low voltage level shifter with pass transistor and reduced-swing output buffer in 65nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65(5), 607–611 (2018)
S.C. Luo, C.J. Huang, Y.H. Chu, A wide-range level shifter using a modified Wilson current mirror hybrid buffer. IEEE Trans. Circuits Syst. I Reg. Briefs 61(6), 1656–1665 (2014)
M. Moghaddam, et al., Low-voltage multi-V\( _{TH} \) single-supply level converters based on CNTFETs, in The 22nd Iranian Conference on Electrical Engineering (ICEE 2014) (2014), pp. 366–370
M. Moghaddam et al., A low-voltage single-supply level converter for sub-VTH /super-VTH operation: 0.3 V to 1.2 V. Int. J. Comput. Appl. 46(2), 0975–8887 (2013)
M. Moghaddam et al., Low-power multiplier using an efficient single-supply voltage level converter. J. Circuits Syst. Comput. 24(8), 1550124 (2015)
M. Morsali, M.H. Moaiyeri, Ultra-high-performance magnetic nonvolatile level converter flip-flop with spin-hall assistance for dual-supply systems with power gating architecture. Circuits Syst. Signal Process. 40, 1383–1396 (2021)
M. Morsali, M.H. Moaiyeri, NVLCFF: an energy-efficient magnetic nonvolatile level converter flip-flop for ultra-low-power design. Circuits Syst. Signal Process. 39, 2841–2859 (2020)
R. Selvakumar, C. Arvind, A 16 ns, 28 fJ Wide-range sub-threshold level converter using low-voltage current mirror. Circuits Syst. Signal Process. 40(3), 1479–1495 (2021)
R. Selvakumar, C. Arvind, Fast and energy-efficient level shifter using split-control driver for mixed-signal systems. Arab. J. Sci. Eng. 46(10), 1656–1665 (2021)
A. Wang, A. Chandrakasan, A 180 mV subthreshold FFT processor using a minimum energy design methodology. IEEE J. Solid-State Circuits 40(1), 310–319 (2005)
L. Wen et al., Sub-threshold level shifter with self-controlled current limiter by detecting output error. IEEE Trans. Circuits Syst. II Express Brief 63(4), 346–350 (2016)
H. You, J. Yuan, W. Tang, S. Qiao, Y. Hei, An energy-efficient level shifter for ultra low-voltage digital LSIs. IEEE Trans. Circuits Syst. II Express Briefs 67(12), 3357–3361 (2020)
W. Zhao, A. Alvarez, Y. Ha, A 65-nm 25.1ns 30.7fJ Robust sub-threshold level shifter with wide conversion range. IEEE Trans. Circuits Syst. II Express Briefs 62(7), 671–675 (2015)
J. Zhou et al., An ultra-low voltage level shifter using revised Wilson current mirror for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage. IEEE Trans. Circuits Syst. I Reg. Briefs 62(3), 697–705 (2015)
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Mayakkannan, A.V., Rajendran, S., Kannan, S. et al. A Split-Input Driver-Enabled High-Speed and Energy-Efficient Level Shifter Using Hybrid Pull-Up Network. Circuits Syst Signal Process 41, 2308–2321 (2022). https://doi.org/10.1007/s00034-021-01864-w
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DOI: https://doi.org/10.1007/s00034-021-01864-w