Abstract
Multipliers are the most demanding component of any filter. They not only dominate most of the chip area but also contribute to most of the computational delay. An efficient realization of filter thus requires optimization of the multipliers. In this paper, a high performance block reconfigurable finite impulse response filter structure is presented. Block-based realization improves the overall throughput of the structure. A novel partial-product-based structure is proposed for Multiply and Accumulation operation, instead of traditional multipliers-based structure. Pipelining and parallelism in the structure improves the throughput of the design. The reuse of the partial products reduces the number of adders and increases the speed, thereby reducing the area-delay product (ADP) and energy-per output (EPO), in comparison with the earlier reported structures. The comparative analysis is done with the help of ASIC synthesis results and the results show that the proposed architecture for filter order 16 and block input 8requires 28.91% less ADP and 25.72% less EPO than the earlier reported architecture.
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D.J. Allred, H. Yoo, V. Krishnan, W. Huang, D.V. Anderson, LMS adaptive filters using distributed arithmetic for high throughput. IEEE Trans. Circuits Syst. I. Reg. Papers 52(7), 1327–1337 (2005)
E. Buracchini, The software radio concept. IEEE Commun. Mag. 38, 138–143 (2000)
H.Q. Cao, W. Li, VLSI implementation of vector quantization using distributed arithmetic. Proc. IEEE Int. Symp. Circuits Syst. 2, 668–671 (1996)
K. H. Chen, T. D. Chiueh, Design and Implementation of A Reconfigurable FIR Filter. IEEE International Symposium on Circuits and Systems, 2003 (ISCAS '03), Bangkok, Thailand, 25–28 (2003).
X. Chenghuan, C. He, Z. Shunan, W. Hua, Design and implementation of a high speed programmable polyphase FIR filter, in Proc. 5th Int. Conf. Applicat.-Specific Integr. Circuit, vol. 2., pp. 783–787 (2003).
C. S. Choi, H. Lee, An reconfigurable FIR filter design on a partial reconfiguration platform, Communications and Electronics, 2006. ICCE '06. First International Conference on. IEEE, 352–355 (2006).
S. J. Darak, S. K. P. Gopi , V. A. Prasad, E. Lai, Low-complexity reconfigurable fast filter bank for multi-standard wireless receivers. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 22(5), 1202–1206 (2014).
S. S. Demirsoy, I. Kale, A. G. Dempster, Efficient implementation of digital filters using novel reconfigurable multiplier blocks, in Proc. 38th Asilomar Conf. Signals Syst. Comput. Conf. Rec., vol. 1. Pacific Grove, CA, USA, pp. 461–464 (2004).
R.I. Hartley, Sub-expression sharing in filters using canonic signed digit multipliers. IEEE Trans. Circuits Syst. II 43(10), 677–688 (1996)
Y. M Hasan, L. J. Karem, M. Falkinburg, A. Helwig, M. Ronning, Canonic signed digit Chebyshev FIR filter design. IEEE Signal Process. Lett., 8(6), 167–169 (2001).
Hentschel, G. Fettweis, Software Radio Receivers, in CDMA Techniques for Third Generation Mobile Systems, Dordrecht, The Netherlands: Kluwer Academic,pp. 257–283,1999.
R. M. Hewlitt, E. S. Swartzlantler, Jr., Canonical Signed Digit Representation for FIR Digital Filters, in Proc. IEEE Worksh. Signal Process. Syst., pp. 416–426 (2000).
K. T. Hong, S. D. Yi, K. M. Chung, A high-Speed Programmable FIR Digital Filter Using Switching Arrays, in Proc. IEEE Asia Pacific Conf. Circuits Syst., pp. 492–495 (1996).
M. Isohookana, T. Kokkonen, P. Leppanen, A. Nykanen, J. Pyhtila, J. Reinila, J. Sillanpaa, and V. Tapio, Software radio-an alternative for the future in wireless personal and multimedia communications, in Proc. IEEE Int. Conf. Personal Wireless Commun., pp. 364–368 (1999).
R. Jia, H.-G. Yang, C.Y. Lin, R. Chen, X.-G. Wang, Z.-H. Guo, A computationally efficient reconfigurable FIR filter architecture based on coefficient occurrence probability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35(8), 1297–1308 (2016).
M. Kumm, K. Moller, P. Zipf, Dynamically reconfigurable FIR filter architectures with fast reconfiguration, in Proc. 8th Int. Workshop ReCoSoC, pp. 1–8, (2013).
R. Mahesh, A. P. Vinod, New reconfigurable architectures for implementing FIR filters with low complexity. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 29(2), 275–288 (2010).
R. Mahesh, A. P. Vinod, A new common subexpression elimination algorithm for realizing low-complexity higher order digital filters. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 27(2), 217–229 (2008).
P. K. Meher, S. Y. Park, High-Throughput Pipelined Realization of Adaptive FIR Filter Based on Distributed Arithmetic, in Proc. IEEE/IFIP 19th Int. Conf. VLSI-SOC, pp. 428–433, (2011).
P. K. Meher, Hardware-Efficient Systolization of DA-Based Calculation of Finite Digital Convolution. IEEE Trans. Circuits Syst. II, Exp. Briefs, 53(8), 707–711, (2006).
P.K. Meher, S. Chandrasekaran, A. Amira, FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic. IEEE Trans. Signal Process. 56(7), 3009–3017 (2008)
S. N. Merchant, B. V. Rao, Distributed Arithmetic Architecture for Image Coding, in Proc. IEEE Int. Conf. TENCON’89, pp. 74–77, (1989).
J. Mitola, Object-Oriented Approaches to Wireless Systems Engineering", Software Radio Architecture (Wiley, New York, 2000)
J. Mitola, The software radio architecture. Commun. Mag. IEEE 33, 26–38 (1995)
B. K. Mohanty, P. K. Meher, A high-performance FIR filter architecture for fixed and reconfigurable applications. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 24(2), 444–452 (2016).
N. Moreano, E. Borin, C. De Souza, G. Araujo, Efficient Datapath Merging for Partially Reconfigurable Architectures. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 24(7), 969–980 (2005).
E. Ozalevli, W. Huang, P.E. Hasler, D.V. Anderson, A reconfigurable mixed-signal VLSI implementation of distributed arithmetic used for finite-impulse response filtering. IEEE Trans. Circuits Syst. I Regul. Pap. 55(2), 510–521 (2008)
S. Y. Park, P. K. Meher, Efficient FPGA and ASIC Realizations of a DA-based reconfigurable FIR digital filter. IEEE Trans. Circuits Syst. II Exp. Briefs, 61(7), 511–515 (2014).
T. Peter, C. Hoe James, P. Markus, Time-multiplexed multiple-constant multiplication. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 26(9), 1551–1563, (2007).
T. Rissa, R. Uusikartano, J. Niittylahti, Adaptive FIR filter architectures for run-time reconfigurable FPGAs,” in Proc. 2002 IEEE Int. Conf. Field Programm. Technol., 52–59, (2002).
M. Tamada, A. Nishihara, High-Speed FIR digital filter with CSD coefficients implemented on FPGA,” in Proc. ASP DAC’01, pp. 7–8, (2001).
P. Tummeltshammer, J. C. Hoe, M. Puschel, Time-multiplexed multiple-constant multiplication. IEEE Trans. Comput. Aided Design. Integr. Circuits, 269, 1551–1563 (2007).
A.P. Vinod, E. Lai, Low power and high speed implementation of FIR filters for software defined radio receivers. IEEE Trans. Wireless Commun. 5(7), 1669–1675 (2006)
S.A. White, Applications of distributed arithmetic to digital signal processing: a tutorial review. IEEE ASSP Mag. 6(3), 4–19 (1989)
T. Zhangwen, Z. Zhanpeng, Z. Jie, M. Hao, A high-speed, programmable, CSD coefficient FIR filter. IEEE Tran. Consumer Electr. 48(4), 834–837 (2002)
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The authors would like to give thanks to Editor-in-Chief and to the anonymous reviewers for their valuable comments and suggestions to improve the quality of this paper.
We further declare that, all data is provided in full in the results section of this paper and this manuscript has no associated data.
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Shrivastava, P.C., Kumar, P., Tiwari, M. et al. An Efficient Block-Based Architecture for Reconfigurable FIR Filter Using Partial-Product Method. Circuits Syst Signal Process 41, 2173–2187 (2022). https://doi.org/10.1007/s00034-021-01881-9
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DOI: https://doi.org/10.1007/s00034-021-01881-9