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A Low-Area Low-Power Column-parallel Digital Decimation Filter Using 1-Bit Pre-BWI Topology for CMOS Image Sensor in 40-nm CMOS Process

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Abstract

A low-area and low-power (LAP) design of second-order digital decimation filter (DDF) with 13-bit dynamic range is proposed in this paper, for column-parallel \(\varSigma \varDelta \) ADC array in CMOS image sensor (CIS). The proposed structure moves the location of the bit-wise-inversion (BWI) cell to the front of the ripple counter and subtracts a fixed array-wise residual value defined by the ADC over-sampling ratio. Then, the number of inverters and multiplexers in the BWI unit is significantly reduced without changing the overall logical functionality of the digital decimation filter. Moreover, an inverted 13-bit register circuit is designed and the transistor number per cell is reduced from 9 to 7, while the sum logic of the 13-bit adder is modified accordingly. A sequential logic front-end circuit is also proposed for input bitstream preprocess and the glitch due to the clock phase misalignment can be eliminated. Compared with prior arts, the transistor usage of the proposed decimation filter topology is significantly reduced to only 292 and the power consumption is also reduced due to the minimized usage of the pre-BWI cell. The area of the proposed decimation filter is about \(4.5\times 32\ {\upmu }\hbox {m}^2\) per column by using a 40-nm CMOS process, and according to the post-layout simulation, the typical power consumption is about \(0.96\ {\upmu }\hbox {W}\) per column at 50-MHz clock frequency.

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Data Availability Statement

The datasets generated during and/or analyzed during the current study are available from the first author on reasonable request.

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Acknowledgements

This work was partly sponsored by Natural Science Foundation of Chongqing, China, No. cstc2019jcyj-zdxmX0014.

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Authors and Affiliations

  1. School of Microelectronics and Communication Engineering, Chongqing University, Room 437, No.4 dormitory building, Area A, No.174, Shazheng street, Shapingba district, Chongqing, 400044, People’s Republic of China

    Peng Yin, Zhongjie Wang, Yingjun Xia, Xiaoping Zeng & Fang Tang

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  1. Peng Yin
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  2. Zhongjie Wang
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  3. Yingjun Xia
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  4. Xiaoping Zeng
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  5. Fang Tang
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Contributions

All authors contributed to the study conception and design. Circuit design, simulation, layout were performed by Peng Yin, Zhongjie Wang, and Yingjun Xia. Professor Fang Tang and Xiaoping Zeng provided experimental platforms for circuit design and professional guidance for the revision of the paper.

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Correspondence to Yingjun Xia or Xiaoping Zeng.

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Yin, P., Wang, Z., Xia, Y. et al. A Low-Area Low-Power Column-parallel Digital Decimation Filter Using 1-Bit Pre-BWI Topology for CMOS Image Sensor in 40-nm CMOS Process. Circuits Syst Signal Process 41, 2681–2698 (2022). https://doi.org/10.1007/s00034-021-01898-0

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