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A 0.6–1.8 V/0.4–1.6 V Input/Output LDO with High PSRR over 50 dB/30 dB in Dual-Modes

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Abstract

A output-capacitorless, wide range 0.6–1.8 V/0.4–1.6 V input/output, dual-mode low-dropout regulator with a high-power supply rejection ratio (PSRR) is proposed in this paper. When the input voltage is higher than 1.2 V, the high-voltage mode (HVM) is activated and the input can be directly used in the proposed LDO with high PSRR and high stability. If the input voltage drops below 1.2 V, LDO would be working stably by the charge pump and internal voltage-controlled oscillator in low-voltage mode (LVM). Meanwhile, linearity and load regulations can also be improved through the proposed sub-amplifier transconductance-enhancement compensation method and high-speed transconductance buffer. The verification of design is completed under a standard 0.18 μm CMOS process. The simulation results show that output voltage ranges from 0.4 to 1.6 V while input ranges from 0.6 to 1.8 V, and proposed LDO remains over 50 dB PSRR in HVM mode and 30 dB in LVM mode.

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Data sharing is not applicable to this article as no datasets were generated or analyzed during the current study.

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Acknowledgements

This work was supported by the National Natural Science Foundation of China (61804124, 61674122) and the Natural Science Project of Shaanxi Province Education Department (18JK0703).

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Authors and Affiliations

  1. School of Electronic Engineering, Xi’an University of Posts & Telecommunications, Xi’an, 710121, China

    Siwan Dong, Sen Bu & Xingyuan Tong

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  1. Siwan Dong
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  2. Sen Bu
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  3. Xingyuan Tong
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Correspondence to Xingyuan Tong.

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Dong, S., Bu, S. & Tong, X. A 0.6–1.8 V/0.4–1.6 V Input/Output LDO with High PSRR over 50 dB/30 dB in Dual-Modes. Circuits Syst Signal Process 42, 84–106 (2023). https://doi.org/10.1007/s00034-022-02147-8

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