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PHetDP: A Placement Algorithm for Heterogeneous FPGAs with Delayed Packing

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Abstract

In this paper, a new wirelength-driven placement model for UltraScale heterogeneous FPGAs have been developed and presented. The proposed algorithm applies a novel approach of utilizing the architectural information of the UltraScale heterogeneous FPGA to guide the placement from the initial stage of the proposed technique. The initial placement is followed by a cluster selection and net selection processes. The novelty of the proposed placement method lies in the fixed block-based cluster formation, segregation table and cell mapping to different placement sites. The segregation table and cell mapping methods are proposed to achieve a good global placement solution by consider a rough legalization and area congestion estimation. A new legalization procedure has been introduced to reduce legalization cost by employing delayed packing and cell mapping to BELs. A detailed placement phase is explored to refine the placement to achieve congestion free legal placement of cells with minimized wirelength. Experimental results have shown that the proposed algorithm achieves better results than the state-of-the-art FPGAs placement algorithms in terms of wirelength without using any expensive optimization framework.

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Data sharing is not applicable to this article as no datasets were generated or analyzed during the current study.

References

  1. Z. Abuowaimer, D. Maarouf, T. Martin, J. Foxcroft, G. Gréwal, S. Areibi, A. Vannelli, GPlace 3.0: Routability-driven analytic placer for UltraScale FPGA architectures. ACM Trans. Design Automation Electr. Syst. 23(5), 1–33 (2018). https://doi.org/10.1145/3233244

    Article  Google Scholar 

  2. A. Agnihotri, M. C. Yildiz, A. Khatkhate, A. Mathur, S. Ono, P. H. Madden, Fractional cut: improved Recursive Bisection Placement. In Proceedings of the 2003 IEEE/ACM international conference on Computer-aided Design, IEEE Computer Society, 307–310 (2003). https://doi.org/10.1109/ICCAD.2003.1257685

  3. A. Alhyari, A. Shamli, Z. Abuwaimer, S. Areibi, G. Grewal, A Deep Learning Framework to Predict Routability for FPGA Circuit Placement. 29th International Conference on Field Programmable Logic and Applications (FPL), 334–341 (2019). https://doi.org/10.1109/FPL.2019.00060

  4. U. Brenner, M. Struzyna, J. Vygen, BonnPlace: Placement of leading-edge chips by advanced combinatorial algorithms. In IEEE Trans. Computer-Aided Design Integrated Circuits Syst 27(9), 1607–1620 (2008). https://doi.org/10.1109/TCAD.2008.927674

    Article  Google Scholar 

  5. U. Brenner, A. Rohe, An effective congestion-driven placement framework. In IEEE Trans Computer-Aided Design Integr Circuits Syst 22(4), 387–394 (2003). https://doi.org/10.1109/TCAD.2003.809662

    Article  Google Scholar 

  6. W. T. J. Chan, Y. Du, A. B. Kahng, S. Nath, K. Samadi, BEOL Stack-aware Routability Prediction from Placement using Data Mining Techniques. IEEE 34th International Conference on Computer Design (ICCD), 41–48 (2016). https://doi.org/10.1109/ICCD.2016.7753259

  7. W.-T. J. Chan, P.-H. Ho, A. B. Kahng, P. Saxena, Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning. In Proceedings of the 2017 ACM on International Symposium on Physical Design (ISPD ’17). Association for Computing Machinery, 15–21 (2017). https://doi.org/10.1145/3036669.3036681

  8. T. Chen, Z. Jiang, T. Hsu, H. Chen, Y. Chang, NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. IEEE Trans. Computer-Aided Design Integr. Circuits Syst. 27(7), 1228–1240 (2008). https://doi.org/10.1109/TCAD.2008.923063

    Article  Google Scholar 

  9. G. Chen, C.-W. Pui, W.-K. Chow, K.-C. Lam, J. Kuang, E.F.Y. Young, B. Yu, Ripplefpga: Routability-driven simultaneous packing and placement for modern FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10), 2022–2035 (2018). https://doi.org/10.1109/TCAD.2017.2778058

    Article  Google Scholar 

  10. S. Chou, M.-K. Hsu, Yao-Wen Chang, Structure-aware placement for datapath-intensive circuit designs. In Proceedings of the 49th Annual Design Automation Conference (DAC ’12). Association for Computing Machinery, 762–767 (2012). https://doi.org/10.1145/2228360.2228498

  11. M. Gort, J. H. Anderson, Analytical placement for heterogeneous FPGAs. 22nd International Conference on Field Programmable Logic and Applications (FPL), 143–150 (2012). https://doi.org/10.1109/FPL.2012.6339278

  12. X. He et al., Ripple 2.0: High quality routability-driven placement via global router integration. 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1–6 (2013). https://doi.org/10.1145/2463209.2488922

  13. M. Kim, D. Lee, I.L. Markov, SimPL: An effective placement algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(1), 50–60 (2012). https://doi.org/10.1109/TCAD.2011.2170567

    Article  Google Scholar 

  14. W. Li, S. Dhar, D.Z. Pan, UTPlaceF: A Routability-Driven FPGA placer with physical and congestion aware packing. IEEE Trans. Computer-Aided Design Integr. Circuits Syst. 37(4), 869–882 (2018). https://doi.org/10.1145/2966986.2980083

    Article  Google Scholar 

  15. W. Li, Y. Lin, D. Z. Pan, elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs. IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 1–8(2019). https://doi.org/10.1109/ICCAD45719.2019.8942075

  16. T.-H. Lin, P. Banerjee, Y. -W. Chang, An efficient and effective analytical placer for FPGAs. 50th ACM/EDAC/IEEE Design Automation Conference (DAC). 1–6 (2013)

  17. D. Maarouf, A. Alhyari, Z. Abuowaimer, T. Martin, A. Gunter, G. Grewal, S. Areibi, A. Vannelli, Machine-learning based congestion estimation for modern FPGAs. In 2018 28th International Conference on Field Programmable Logic and Applications (FPL). 427–4277 (2018). https://doi.org/10.1109/FPL.2018.00079

  18. M. Pan, C. Chu, IPR: An Integrated Placement and Routing Algorithm. 44th ACM/IEEE Design Automation Conference. 59–62 (2007). https://doi.org/10.1145/1278480.1278496

  19. C. -W. Pui, G. Chen, Y. Ma, E. F. Y. Young, B. Yu, Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 929–936 (2017)

  20. H. Szentimrey, A. Al-Hyari, J. Foxcroft, T. Martin, D. Noel, G. Grewal, S. Areibi, Machine learning for congestion management and routability prediction within FPGA placement. ACM Trans. Des. Autom. Electron. Syst. 25(5), 1–25 (2020). https://doi.org/10.1145/3373269

    Article  Google Scholar 

  21. K. Vorwerk, A. Kennings, An improved multi-level framework for force-directed placement. Design Automation Test Euro. 2, 902–907 (2005). https://doi.org/10.1109/DATE.2005.59

    Article  Google Scholar 

  22. D. Xie, J. Xu, J. Lai, A New FPGA placement algorithm for heterogeneous resources. IEEE 8th International Conference on ASIC. 742-746 (2009). https://doi.org/10.1109/ASICON.2009.5351312

  23. S. Yang, A. Gayasen, C. Mulpuri, S. Reddy, R. Aggarwal, Routability-Driven FPGA Placement Contest. In Proceedings of the 2016 on International Symposium on Physical Design. Association for Computing Machinery, 139–143 (2016). https://doi.org/10.1145/2872334.2886419

  24. inc Xilinx. http://www.xilinx.com

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Acknowledgements

The authors would like to acknowledge the Department of CSE and the IoT Laboratory, NIT Silchar for providing research atmosphere and infrastructure necessary for this work.

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Correspondence to Shyamapada Mukherjee.

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Purkayastha, S., Mukherjee, S. PHetDP: A Placement Algorithm for Heterogeneous FPGAs with Delayed Packing. Circuits Syst Signal Process 42, 801–827 (2023). https://doi.org/10.1007/s00034-022-02159-4

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