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A Trainable Synapse Circuit Using a Time-Domain Digital-to-Analog Converter

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Abstract

We propose a CMOS synapse circuit using a time-domain digital-to-analog converter (TDAC) for realizing spiking neural network hardware with on-chip learning. A TDAC has the advantages that (i) it can reproduce a post-synaptic potential and (ii) its number of analog components for DA conversion, such as current sources and capacitors, is independent of the bit width. We designed a synapse circuit using TSMC 40 nm technology, and the synaptic weight was updated by the remote supervised method (ReSuMe) or spike timing-dependent plasticity (STDP). The circuit simulation results of the designed circuit show that it can execute ReSuMe and generate the time-window function for STDP with high energy efficiency.

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Acknowledgements

This work was supported by the VLSI Design and Education Center (VDEC), the University of Tokyo, in collaboration with Cadence Design Systems, Inc., AMED under Grant Number JP20dm0307009, UTokyo Center for Integrative Science of Human Behavior (CiSHuB), the International Research Center for Neurointelligence (WPI-IRCN) at The University of Tokyo Institutes for Advanced Study (UTIAS), and by the BMAI(BrainMorphic AI) project at Institute of Industrial Science, the University of Tokyo in collaboration with NEC Corporation.

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Correspondence to Seiji Uenohara.

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Uenohara, S., Aihara, K. A Trainable Synapse Circuit Using a Time-Domain Digital-to-Analog Converter. Circuits Syst Signal Process 42, 1312–1326 (2023). https://doi.org/10.1007/s00034-022-02168-3

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