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High-performance intra-mode accelerator for HEVC

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Abstract

The high efficiency video coding (HEVC/H.265) is the latest coding standard that reduces the bit-rate requirement by 50% compared to its predecessor, i.e., H.264. However, the coding complexity of HEVC is increased a lot not only due to its increased number of intra-modes (35 in total), but also due to its brute force methodology. In this article, a fast intra-mode decision strategy is proposed to reduce the complexity of HEVC. The proposed work first incorporates the statistical inference that was formed using the spatial/temporal data into the HEVC’s rough-mode-decision module. Then early termination is predicted by proposing a model that is based on the classical secretary problem (CSP). Thirdly, the uncertainty of the real world is introduced to the proposed CSP that outperforms the existing CSPs. Simulation results demonstrate that the proposed model is capable of achieving a minimum of 32.39% reduction in the total encoding time while the bit-rate (BD-BR) increment is limited to 1.33% on average.

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  1. Department of Computer Science and Engineering, HITEC University, Taxila, Pakistan

    Junaid Tariq

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  1. Junaid Tariq
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Tariq, J. High-performance intra-mode accelerator for HEVC. Vis Comput 36, 1603–1617 (2020). https://doi.org/10.1007/s00371-019-01764-w

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