Abstract
We study the following optimization problem. The input is a number \(k\) and a directed graph with a specified “start” vertex, each of whose vertices may have one “memory bank requirement”, an integer. There are \(k\) “registers”, labeled \(1, \ldots , k\). A valid solution associates to the vertices with no bank requirement one or more “load instructions” \(L[b,j]\), for bank \(b\) and register \(j\), such that every directed trail from the start vertex to some vertex with bank requirement \(c\) contains a vertex \(u\) that has been associated \(L[c,i]\) (for some register \(i \le k\)) and no vertex following \(u\) in the trail has been associated an \(L[b,i]\), for any other bank \(b\). The objective is to minimize the total number of associated load instructions. We give a \(k(k+1)\)-approximation algorithm based on linear programming rounding, with \((k+1)\) being the best possible unless Vertex Cover has approximation \(2 - {\epsilon }\) for \({\epsilon }> 0\). We also present a \(O(k \log n)\) approximation, with \(n\) being the number of vertices in the input directed graph. Based on the same linear program, another rounding method outputs a valid solution with objective at most \(2k\) times the optimum for \(k\) registers, using \(2k-1\) registers.
Similar content being viewed by others
References
Alon, N., Joel, H.: Spencer. The probabilistic method, 2nd edn. Wiley, Hoboken, NJ (2000)
Amit, A., Noga, A., Moses, S.: Charikar. Improved approximation for directed cut problems. In: Proceedings of the thirty-ninth annual ACM symposium on Theory of Computing, STOC ’07, pp. 671–680. ACM, New York, NY (2007)
Bergner, P., Dahl, P., Engebretsen, D., O’Keefe, M.: Spill code minimization via interference region spilling. In: Proceedings of the ACM SIGPLAN 1997 conference on Programming Language Design and Implementation, PLDI ’97, pp. 287–295. ACM, New York, NY (1997)
Bernstein, D., Golumbic, M., Mansour, Y., Pinter, R., Goldin, D., Krawczyk, H. Nahshon, I.: Spill code minimization techniques for optimizing compliers. In: Proceedings of the ACM SIGPLAN 1989 Conference on Programming Language Design and Implementation, PLDI ’89, pp. 258–263. ACM, New York, NY (1989)
Briggs, P., Cooper, K.D., Torczon, L.: Coloring register pairs. ACM Lett. Program. Lang. Sys. 1, 3–13 (1992)
Changqing, Fu., Wilken, K.: A faster optimal register allocator. In: Proceedings of the 35th annual ACM/IEEE International symposium on Microarchitecture, MICRO 35, pp. 245–256. IEEE Computer Society Press, Los Alamitos, CA (2002)
Charikar, M., Chekuri, C., Cheung, T.Y., Dai, Z., Goel, A., Guha, Sudipto, Li, Ming: Approximation algorithms for directed Steiner problems. J. Algo. 33(1), 73–91 (1999)
Cheriyan, J., Karloff, H.J., Rabani, Y.: Approximating directed multicuts. Combinatorica 25(3), 251–269 (2005)
Cooper, K., Dasgupta, A., Eckhardt, J.: Revisiting graph coloring register allocation: a study of the Chaitin–Briggs and Callahan–Koblenz algorithms. In: Ayguad, E., Baumgartner, G., Ramanujam, J., Sadayappan, P., (eds) Languages and Compilers for Parallel Computing, Lecture Notes in Computer Science, vol. 4339, pp. 1–16. Springer, Berlin (2006)
Dinur, I., Guruswami, V., Khot, S., Regev, O.: A new multilayered PCP and the hardness of hypergraph vertex cover. SIAM J. Comput. 34(5), 1129–1146 (2005)
Falk, H.: Wcet-aware register allocation based on graph coloring. In: Proceedings of the Fourty-Sixth ACM/IEEE Design Automation Conference, DAC’09. ACM, New York , NJ (2009)
Freescale. http://www.freescale.com
Garg, N., Vazirani, V.V., Yannakakis, M.: Multiway cuts in node weighted graphs. J. Algo. 50(1), 49–61 (2004)
Gupta, A.: Improved results for directed multicut. In: Proceedings of the fourteenth annual ACM-SIAM symposium on Discrete algorithms, SODA ’03, pp. 454–455. Society for Industrial and Applied Mathematics, Philadelphia, PA (2003)
Jansen, K.: The allocation problem in hardware design. Discret. Appl. Math. 43(1), 37–46 (1993)
Jansen, K., Reiter, J.: An approximation algorithm for the register allocation problem. Int. VLSI J. 25(2), 89–102 (1998)
Jansen, K., Porkolab, L.: On preemptiveresource constrained scheduling: polynomial-time approximation schemes. SIAM J. Discret. Math. 20(3), 545–563 (2006)
Kannan, S., Proebsting, T.A.: Register allocation in structured programs. J. Algo. 29(2), 223–237 (1998)
Koes, D.R., Goldstein, S.C.: A global progressive register allocator. In: Proceedings of the ACM SIGPLAN 2006 conference on Programming language design and implementation, PLDI ’06, pp. 204–215. ACM, New York, NY (2006)
Koes, D., Goldstein, S.C.: A progressive register allocator for irregular architectures. In: Proceedings of the International Symposium on Code Generation and Optimization, CGO ’05, pp. 269–280. IEEE Computer Society, Washington, DC (2005)
Koes, D.R., Goldstein, S.C.: Register allocation deconstructed. In: Proceedings of the 12th International Workshop on Software and Compilers for Embedded Systems, SCOPES ’09, pp. 21–30. ACM, New York, NY (2009)
Li, M., Chun Jason, X., Tiantian, L., Yingchao, Z.: Analysis and approximation for bank selection instruction minimization on partitioned memory architecture. J. Comb. Optim. 23(2), 274–291 (2012)
Plotkin, S.A., Shmoys, D.B., Tardos, E.: Fast approximation algorithms for fractional packing and covering problems. Math. Oper. Res. 20, 257–301 (1995)
Quintão Pereira, F.M., Pereira, J. Palsberg.: Register allocation by puzzle solving. In: Proceedings of the 2008 ACM SIGPLAN conference on Programming Language Design and Implementation, PLDI ’08, pp. 216–226. ACM, New York, NY (2008)
Sleator, D.D., Tarjan, R.E.: Amortized efficiency of list update and paging rules. Commun. ACM 28(2), 202–208 (1985)
Smith, M.D., Ramsey, N., Holloway, G.: A generalized algorithm for graph-coloring register allocation. In: Proceedings of the ACM SIGPLAN 2004 conference on Programming Language Design and Implementation, PLDI ’04, pp. 277–288. ACM, New York, NY (2004)
Thorup, M.: All structured programs have small tree-width and good register allocation. Inf. Comput. 142(2), 159–181 (1998)
Zalamea, J., Llosa, J., Ayguad, E., Valero, M.: Modulo scheduling with integrated register spilling. In: Dietz, H. (ed.) Languages and Compilers for Parallel Computing. Lecture Notes in Computer Science, vol. 2624, pp. 239–253. Springer, Berlin (2003)
Zelikovsky, A.: A series of approximation algorithms for the acyclic directed Steiner tree problem. Algorithmica 18(1), 99–110 (1997)
Zhou, Y.: Hardness of register loading, 2010. Personal communication (2010)
Zilog.: http://www.zilog.com
Zosin, L., Khuller, S.: On directed Steiner trees. In: Proceedings of the Thirteenth Annual ACM-SIAM Symposium on Discrete Algorithms, SODA’02, pp. 59–63. Society for Industrial and Applied Mathematics, San Francisco, CA (2002)
Acknowledgments
Research supported in part by NSF Grant NeTS-0916743 and a grant from the Research grants Council of the Hong Kong Special Administrative Region, China [Project No. CityU 124411].
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Calinescu, G., Li, M. Register Loading via Linear Programming. Algorithmica 72, 1011–1032 (2015). https://doi.org/10.1007/s00453-014-9888-2
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00453-014-9888-2