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Building reliable systems-on-chip in nanoscale technologies

Der Entwurf zuverlässiger Systems-on-Chip in Nanotechnologie

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Abstract

Modern application-specific integrated circuits (ASICs) contain complete systems on a single die, composed of many processing elements that communicate over a dedicated router-based on-chip network. As systems-on-chip comprise billions of transistors with feature sizes in the range of 10 nm, reliable operation cannot be established without carefully engineered support at all levels, from technology to the circuit- and the system-layer. This article surveys contributions of research groups at TU Wien to this field. At lower levels of abstraction, they range from the generation of fault models for simulation that closely match reality and are at the same time efficient to use, to circuit-level radiation-tolerance techniques. At the level of on-chip networks, novel fault-tolerant routing algorithms are being developed together with architectural techniques to isolate faulty parts while keeping the healthy parts connected and active.

The article will briefly portray the associated research activities and summarize their most relevant results.

Zusammenfassung

Moderne anwendungsspezifische integrierte Schaltungen (ASICs) beinhalten auf einem einzigen Chip ganze Systeme, bestehend aus einer Vielzahl an Funktionsblöcken, die über eigene Router-basierte “On-chip”-Netzwerke kommunizieren. Der zuverlässige Betrieb eines solchen Milliarden an Transistoren mit Feature-Size in Bereich von 10 nm umfassenden Systems kann nur durch sorgfältig ausgelegte Maßnahmen auf allen Ebenen, von der Technologie über das Schaltungsdesign bis hin zur Systemebene, gewährleistet werden. Der vorliegende Artikel gibt einen Überblick über die diesbezüglichen Beiträge der Forschergruppen an der TU Wien. Auf den unteren Abstraktionsebenen reichen diese von der Erstellung möglichst wirklichkeitsgetreuer Fehlermodelle für die Simulation, die dennoch handhabbar bleiben, bis hin zu schaltungstechnischen Maßnahmen zur Erhöhung der Strahlungsfestigkeit. Auf der Ebene der On-chip-Netzwerke werden neuartige fehlertolerante Routing-Algorithmen in Kombination mit Architekturmaßnahmen entwickelt, die fehlerhafte Bereiche isolieren, während funktionierende Teile verbunden und aktiv bleiben.

Der Artikel umreißt die entsprechenden Forschungsaktivitäten und skizziert ihre wichtigsten Ergebnisse.

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Notes

  1. The project “Fault-Tolerant Asynchronous Logic (FATAL)” was a joint FWF basic research project (P21694) of TU Wien Institute of Computer Engineering and the Institute of Electrodynamics, Microwave and Circuit Engineering. It started in October 2009 and ended in March 2014; its SET-related part is now continued in the FWF basic research project EASET (P26435).

  2. We performed radiation experiments at GSI in Darmstadt, PTB in Braunschweig and SNAKE in Munich.

  3. The project “Accelerator-based Experimental Analysis and Simulation Modeling of Single-Event-Transients in VLSI Circuits (EASET)” is a joint FWF basic research project (P25218) of TU Wien Institute of Computer Engineering and the Institute of Electrodynamics, Microwave and Circuit Engineering. It started in April 2014.

  4. We are grateful for the funding from TU Wien that we received for this purpose in the framework of the innovative project “Robust Nanoscale Logic Devices”.

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Steininger, A., Zimmermann, H., Jantsch, A. et al. Building reliable systems-on-chip in nanoscale technologies. Elektrotech. Inftech. 132, 301–306 (2015). https://doi.org/10.1007/s00502-015-0319-0

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