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System on chip failure rate assessment using the executable model of a system

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Abstract

Statistical data from many application fields confirm that System on Chips (SoCs) products implemented in modern deep submicron technologies are getting more and more sensitive to transient errors such as soft-errors. Although the thorough and comprehensive understanding of services that an SoCs provides is an important step for meeting stringent system requirements, designers no longer can ignore emerging safety and reliability issues in nanoscale devices. In fact, proper actions should be taken at various stages of system design to mitigate the effect of such errors and enhance safety of SoC in fault prone environments. Therefore, SoC designs can benefit from knowing the soft-error rate (SER) of different cores as well as the whole system failure rate at a very early stage of SoC development. Such data enables companies and designers to make the right decision at the right time concerning the intensity of error protection mechanisms across different modules. This paper proposes a new quantitative method to estimate the SER of different modules inside an SoC by means of an executable model. The executable model of a system is based on the Unified Modeling Language Real-Time standard and is exercised by the actual workload. Experimental results show that the proposed quantitative method is 17 % more accurate than the previous error estimations techniques.

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  1. Department of Electrical Engineering, McGill University, Montreal, Canada

    M. H. Neishaburi & Zeljko Zilic

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  1. M. H. Neishaburi
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  2. Zeljko Zilic
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Correspondence to M. H. Neishaburi.

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Neishaburi, M.H., Zilic, Z. System on chip failure rate assessment using the executable model of a system. Computing 97, 611–629 (2015). https://doi.org/10.1007/s00607-013-0372-7

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