Abstract
The demand for safety of electronic devices is high. Especially in safety-critical systems, e.g. electronic railway interlocking systems, safety is an important issue. Nowadays these systems are tested and simulated with a manually created set of test cases. But testing is a very cost-intensive procedure and can never reach a complete coverage for large designs. Hence, an efficient way to formally verify these systems is required. In this paper we present a formal verification flow, including the modeling, for counting heads (CHs) for railways, a real-time system that is used in most electronic railway interlocking systems from SIEMENS.1 The approach shown here is based on SystemC, a powerful system description language. In this way efficient modeling and simulation-based verification of railway components and systems becomes possible. For the formal verification part bounded model checking algorithms are applied, i.e. a set of properties is formally proven to be correct. Additionally the completeness of this set is formally and efficiently determined.
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References
Accellera. Property Specification Language Version 1.1, 2004
Biere, A., Cimatti, A., Clarke, E.M., Fujita, M., Zhu, Y.: Symbolic model checking using SAT procedures instead of BDDs. In: Design Automation Conference, pp. 317–320 (1999)
Burch, J.R., Clarke, E.M., McMillan, K.L., Dill, D.L.: Sequential circuit verification using symbolic model checking. In: Design Automation Conference, pp. 46–51, 1990
Cimatti, A., austo, F., Giunchiglia, G. iorgio Mongardi, ario Romano, D., Torielli, F., Traverso, P.: Model checking safety critical software with spin: An application to a railway interlocking system. In: International Conference on Computer Safety, Reliability and Security, SAFECOMP, pp. 284–295 (1998)
Drechsler R., Große D.: System level validation using formal techniques. IEE Proc. Comp. Digital Tech. Spec. Issue Embedded Microelectr. Syst. Status Trends 152(3), 393–406 (2005)
Eisner, C.: Using symbolic model checking to verify the railway stations of Hoorn–Kersenboogerd and Heerhugowaard. In: Conference on Correct Hardware Design and Verification Methods, pp. 97–109 (1999)
Faber, J., Meyer, R.: Model checking data-dependent real-time properties of the european train control system. In: Formal Methods in Computer Aided Design, pp. 76–77 (2006)
Fey, G., Große, D., Cassens, T., Genz, C., Warode, T., Drechsler, R.: ParSyC: An Efficient SystemC Parser. In: Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 148–154 (2004)
Fokkink, W.J.: Safety criteria for the vital processor interlocking at Hoorn–Kersenboogerd. In: Conference on Computers in Railways, COMPRAIL’96, pp. 101–110 (1996)
Fokkink, W.J., Hollingshead, P.R.: Verification of interlockings: from control tables to ladder logic diagrams. In: Workshop on Formal Methods for Industrial Critical Systems (FMICS), pp. 171–185 (1998)
Große, D., Kühne, U., Drechsler, R.: Estimating functional coverage in bounded model checking. In: Design, Automation and Test in Europe, pp. 1176–1181 (2007)
Groote, J.F., Koorn, J.W.C., van Vlijmen, S.F.M.: The safety guaranteeing system at station hoorn-kersenboogerd. In: Compass ’95: 10th Annual Conference on Computer Assurance, pp. 57–68 (1995)
Grötker T., Liao S., Martin G., Swan S.: System Design with SystemC. Kluwer, Dordrecht (2002)
Hartonas-Garmhausen V., Campos S., Cimatti A., Clarke E., Giunchiglia F.: Verification of a safety-critical railway interlocking system with real-time constraints. Sci. Comp. Program. 36(1), 53–64 (2000)
Siemens, A.G.: Az S M Multiple-section Axle Counting System. Copyright, Siemens AG (2003)
Siemens, A.G.: Transportation Systems, Rail Automation. Safety for the Rail Services. http://www.siemenstransportation.co.uk/pdfs/AzSM\%20R.pdf
Stålmarck, G., Säflund, M.: Modelling and verifying systems and software in propositional logic. In: Symposium on Safety of Computer Control Systems, SAFECOMP, pp. 31–36 (1990)
Synopsys. Describing Synthesizable RTL in SystemCTM, Vers. 1.1. Synopsys Inc., 2002. Available at http://www.synopsys.com
Winkelmann, K., Trylus, H.-J., Stoffel, D., Fey, G.: Cost-efficient block verification for a UMTS up-link chip-rate coprocessor. In: Design, Automation and Test in Europe, vol. 1, pp. 162–167 (2004)
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This work was partly supported by the Rail Automation Graduate School (RA:GS!) of Siemens Transportation System in Braunschweig.
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Kinder, S., Drechsler, R. Modeling and proving functional completeness in formal verification of counting heads. Int J Softw Tools Technol Transfer 10, 521–534 (2008). https://doi.org/10.1007/s10009-008-0084-z
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DOI: https://doi.org/10.1007/s10009-008-0084-z