Abstract
Modern microprocessor design relies heavily on detailed full-chip performance simulations to evaluate complex trade-offs. Typically, different design alternatives are tried out for a specific sub-system or component, while keeping the rest of the system unchanged. We observe that full-chip simulations for such studies is overkill. This paper introduces mesoscale simulation, which employs high-level modeling for the unchanged parts of a design and uses detailed cycle-accurate simulations for the components being modified. This combination of high-level and low-level modeling enables accuracy on par with detailed full-chip modeling while achieving much higher simulation speeds than detailed full-chip simulations. Consequently, mesoscale models can be used to quickly explore vast areas of the design space with high fidelity. We describe a proof-of-concept mesoscale implementation of the memory subsystem of the Cell/B.E. processor and discuss results from running various workloads.
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Communicated by Dr. Raffaela Mirandola and David Lilja.
T. Kiss participated in this work while working at IBM Germany Research & Development, Boeblingen, Germany. R. Rangan participated in this work while working at IBM Research in Austin, TX.
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Altevogt, P., Kiss, T., Kistler, M. et al. Mesoscale performance simulation of multicore processor systems. Softw Syst Model 12, 731–744 (2013). https://doi.org/10.1007/s10270-012-0231-6
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DOI: https://doi.org/10.1007/s10270-012-0231-6