Abstract
Heuristic local search algorithms have achieved good results in tackling combinatorial optimization problems, such as Travelling Salesman Problem (TSP). One of the well-known local search algorithms is the 2-opt algorithm. As a local search algorithm, 2-opt has achieved approximate optimal solutions for TSP within a reasonable time, especially for small data instances. However, solving large data instances of TSP using 2-opt requires extensive computation and considerable CPU time. Therefore, this paper presents a parallel version of the 2-opt algorithm, exploiting the features of Optical Transpose Interconnection System (OTIS) in solving the TSP. In this paper, we present the Parallel Repetitive 2-Opt (PRTO) algorithm for solving symmetric TSP on OTIS Hyper Hexa-Cell (OTIS-HHC) and OTIS Mesh of Trees (OTIS-MOT) optoelectronic architectures. We assess the performance of our algorithm analytically in terms of parallel time complexity, speedup, efficiency, cost, and communication cost on both optoelectronic architectures. Furthermore, a set of simulation experiments is conducted on various instances from the standard TSP library. The simulation results confirm that our algorithm is efficient regarding speedup and efficiency. For instance, the PRTO algorithm achieves a speedup of 32.9 for 6880 cities over OTIS-HHC with 36 processors. Moreover, the superiority of PRTO algorithm is shown through solving the TSP on OTIS-HHC and OTIS-MOT; its performance has been compared with the performance of the Parallel Repetitive Nearest Neighbor (PRNN) algorithm in terms of speedup, efficiency, and solution quality. For example, as a best case, the PRTO algorithm has shown 34 times improved speedup over the PRNN algorithm.
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The authors would like to express their deep gratitude to the anonymous referees for their valuable comments and suggestions, which enhanced this research manuscript.
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Al-Adwan, A., Sharieh, A. & Mahafzah, B.A. Parallel heuristic local search algorithm on OTIS hyper hexa-cell and OTIS mesh of trees optoelectronic architectures. Appl Intell 49, 661–688 (2019). https://doi.org/10.1007/s10489-018-1283-2
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DOI: https://doi.org/10.1007/s10489-018-1283-2