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Active-learning-based reconstruction of circuit model

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Abstract

Reconstructing the circuit model presents a challenge for circuits with unknown functional specifications. The circuit is thought of as a black box that, given an input, produces an output. The model of the circuit, on the other hand, is unknown. Given a set of inputs and their corresponding outputs, the goal is then to recover the circuit specification while maximizing reconstruction accuracy. This process is computationally difficult, and it becomes even more difficult to solve when only a subset of inputs and outputs are provided, as is the case in many large and complex circuits. This issue is addressed in this paper: Reconstructing the model of a circuit from a set of components and observations describing its inputs and outputs. Previous work proposed a decision tree approach, but this approach only works when the entire set of inputs and outputs is available. Nonetheless, for most systems, this requirement is unrealistic. To address this challenge, we propose an active learning approach and applying orthogonal arrays of fractional factorial design to sample labeled data for learning the reconstructed circuit. Evaluation on 9 well known circuits shows the benefits of the proposed algorithms in terms of accuracy, run time and the reconstructed circuit model.

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References

  1. Asha S, Hemamalini RR (2015) Synthesis of adder circuit using cartesian genetic programming. Middle-East J Sci Res 23(6):1181–1186

    Google Scholar 

  2. Atlas LE, Cohn DA, Ladner RE (1990) Training connectionist networks with queries and selective sampling. In: Advances in neural information processing systems, pp 566–573

  3. Brayton RK, Hachtel GD, McMullen C, Sangiovanni-Vincentelli A (1984) Logic minimization algorithms for VLSI synthesis, vol 2. Springer Science & Business Media, Berlin

    Book  Google Scholar 

  4. Demmler D, Dessouky G, Koushanfar F, Sadeghi AR, Schneider T, Zeitouni S (2015) Automated synthesis of optimized circuits for secure computation. In: Proceedings of the 22nd ACM SIGSAC conference on computer and communications security. ACM, pp 1504–1517

  5. Duarte-Villaseñor M. A, Tlelo-Cuautle E, De la Fraga LG (2012) Binary genetic encoding for the synthesis of mixed-mode circuit topologies. Circuits Syst Signal Process 31(3):849–863

    Article  MathSciNet  Google Scholar 

  6. Gan Z, Shang T, Shi G, Chen C (2008) Automatic synthesis of combinational logic circuit with gene expression-based clonal selection algorithm. In: 2008 Fourth international conference on natural computation, vol 6. IEEE, pp 278–282

  7. Gan Z, Shang T, Shi G, Jiang M (2009) Evolutionary design of combinational logic circuits using an improved gene expression-based clonal selection algorithm. In: 2009 Fifth international conference on natural computation, vol 4. IEEE, pp 37–41

  8. Garud SS, Karimi IA, Kraft M (2017) Design of computer experiments: a review. Comput Chem Eng 106:71–95

    Article  Google Scholar 

  9. Hedayat AS, Sloane NJA, Stufken J (2012) Orthogonal arrays: theory and applications. Springer Science & Business Media, Berlin

    MATH  Google Scholar 

  10. Hong SJ, Muroga S (1991) Absolute minimization of completely specified switching functions. IEEE Trans Comput 40(1):53–65

    Article  MathSciNet  Google Scholar 

  11. Li W, Wasson Z, Seshia SA (2012) Reverse engineering circuits using behavioral pattern mining. In: 2012 IEEE International symposium on hardware-oriented security and trust. IEEE, pp 83–88

  12. Lin SY, Fang YC, Li YC, Liu YC, Yang TS, Lin SC, Li CM, Fang EJW (2018) Ir drop prediction of eco-revised circuits using machine learning. In: 2018 IEEE 36Th VLSI test symposium (VTS). IEEE, pp 1–6

  13. Liu D, Yu C, Zhang X, Holcomb D (2016) Oracle-guided incremental sat solving to reverse engineer camouflaged logic circuits. In: 2016 Design, automation & test in europe conference & exhibition (DATE). IEEE, pp 433–438

  14. Mayer UF, Sarkissian A (2003) Experimental design for solicitation campaigns. In: Proceedings of the ninth ACM SIGKDD international conference on knowledge discovery and data mining. ACM, pp 717–722

  15. McCluskey EJ Jr (1956) Minimization of boolean functions. Bell Syst Technic J 35(6):1417–1444

    Article  MathSciNet  Google Scholar 

  16. Melnikov AA, Nautrup HP, Krenn M, Dunjko V, Tiersch M, Zeilinger A, Briegel HJ (2018) Active learning machine learns to create new quantum experiments. Proc Nat Acad Sci 115(6):1221–1226

    Article  Google Scholar 

  17. Montgomery DC (2017) Design and analysis of experiments. Wiley, New York

    Google Scholar 

  18. Nane R, Sima VM, Pilato C, Choi J, Fort B, Canis A, Chen YT, Hsiao H, Brown S, Ferrandi F et al (2015) A survey and evaluation of fpga high-level synthesis tools. IEEE Trans Comput-Aided Design Integrat Circuits Syst 35(10):1591–1604

    Article  Google Scholar 

  19. Plutowski M, White H (1993) Selecting concise training sets from clean data. IEEE Trans Neural Netw 4(2):305–318

    Article  Google Scholar 

  20. Pradhan M, Bhattacharya BB (2019) A prufer-sequence based representation of large graphs for structural encoding of logic networks. In: Proceedings of the ACM India joint international conference on data science and management of data. ACM, pp 293–296

  21. Rada R, Mili H, Bicknell E, Blettner M (1989) Development and application of a metric on semantic nets. IEEE Trans Syst Man Cybern 19(1):17–30

    Article  Google Scholar 

  22. Rematska G, Bourbakis NG (2016) A survey on reverse engineering of technical diagrams. In: 2016 7Th international conference on information, intelligence, systems & applications (IISA). IEEE, pp 1–8

  23. Robbins H (1952) Some aspects of the sequential design of experiments. Bull Am Math Soc 58 (5):527–535

    Article  MathSciNet  Google Scholar 

  24. Rojec ž, Bűrmen Á, Fajfar I (2019) Analog circuit topology synthesis by means of evolutionary computation. Eng Appl Artif Intell 80:48–65

    Article  Google Scholar 

  25. Rokach L, Kalech M, Provan G, Feldman A (2013) Machine-learning-based circuit synthesis. In: Twenty-third international joint conference on artificial intelligence

  26. Rokach L, Naamani L, Shmilovici A (2008) Pessimistic cost-sensitive active learning of decision trees for profit maximizing targeting campaigns. Data Min Knowl Disc 17(2):283–316

    Article  MathSciNet  Google Scholar 

  27. Roth JP (1958) Algebraic topological methods for the synthesis of switching systems. i. Trans Am Math Soc 88(2):301–326

    Article  MathSciNet  Google Scholar 

  28. Rouhani BD, Riazi MS, Koushanfar F (2018) Deepsecure: Scalable provably-secure deep learning. In: Proceedings of the 55th annual design automation conference. ACM, p 2

  29. Settles B (2012) Active learning. Synthesis Lect Artif Intell Mach Learn 6(1):1–114

    Article  MathSciNet  Google Scholar 

  30. Shannon CE (1948) A mathematical theory of communication. Bell Syst Technic J 27(3):379–423

    Article  MathSciNet  Google Scholar 

  31. Sloane NJ (2007) A library of orthogonal arrays. Fixed-level arrays with more than three levels: OA. 16(4.2)

  32. Smith J, Oler K, Miller C, Manz D (2017) Reverse engineering integrated circuits using finite state machine analysis. In: Proceedings of the 50th Hawaii international conference on system sciences

  33. Storck J, Hochreiter S, Schmidhuber J (1995) Reinforcement driven information acquisition in non-deterministic environments. In: Proceedings of the international conference on artificial neural networks, Paris, vol. 2. Citeseer, pp 159–164

  34. Tyasnurita R, Özcan E, John R (2017) Learning heuristic selection using a time delay neural network for open vehicle routing. In: 2017 IEEE Congress on evolutionary computation (CEC). IEEE, pp 1474–1481

  35. Villa T, Sangiovanni-Vincentelli A (1990) Nova: state assignment of finite state machines for optimal two-level logic implementation. IEEE Trans Comput-Aided Design Integrat Circuits Syst 9(9):905–924

    Article  Google Scholar 

  36. Wille R, Drechsler R (2009) Bdd-based synthesis of reversible logic for large functions. In: Proceedings of the 46th annual design automation conference, pp 270–275

  37. Xia X, Song X, Luan F, Zheng J, Chen Z, Ma X (2018) Discriminative feature selection for on-line signature verification. Pattern Recogn 74:422–433

    Article  Google Scholar 

  38. Yang Y, Ma Z, Nie F, Chang X, Hauptmann AG (2015) Multi-class active learning by uncertainty sampling with diversity maximization. Int J Comput Vis 113(2):113–127

    Article  MathSciNet  Google Scholar 

  39. Yu C, Ciesielski M, Mishchenko A (2017) Fast algebraic rewriting based on and-inverter graphs. IEEE Trans Comput-Aided Design Integrat Circuits Syst 37(9):1907–1911

    Article  Google Scholar 

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Correspondence to Gal Rozenfeld.

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Rozenfeld, G., Kalech, M. & Rokach, L. Active-learning-based reconstruction of circuit model. Appl Intell 52, 5125–5143 (2022). https://doi.org/10.1007/s10489-021-02700-z

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