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HALO: a fast and durable disk write cache using phase change memory

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Abstract

To close the increasing performance gap between disk storage and processors, flash based solid-state devices (FSSDs) have been adopted within the memory hierarchy to improve the performance of hard disk drive (HDD) based storage system. However, FSSDs still suffer from erase-before-write restriction, coarse access granularity and limited write endurance. Recently, the cutting-edge non-volatile memory technologies are merging, e.g., phase-change memory and resistive memory, which offer us new storage alternatives with faster access, byte-addressability and better endurance. In order to address the imperative data intensive computing issues, we propose to leverage PCM as disk write cache for constructing a hybrid PCM+HDD storage architecture in this paper. First, we develop a novel hash-based write caching scheme called HALO to improve both spatial and temporal locality on hard disks, thus addressing the limitations of traditional LRU caching algorithms and rendering better I/O performance. To deal with the limited durability of PCM devices and reclaim the degraded spatial locality in previous wear-leveling techniques, we further propose novel PCM wear leveling algorithms that provide effectively uniform writes while maximizing access parallelism. We have evaluated this PCM-based hybrid storage architecture using applications with a diverse set of I/O access patterns. Our experimental results demonstrate that the HALO caching scheme leads to an average reduction of 36.8% in execution time compared to the LRU caching scheme, and that the space filling curve based wear leveling extends the lifetime of PCM by a factor of 21.6.

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References

  1. Akel, A., Caulfield, A., Mollov, T., Gupta, R., Swanson, S.: Onyx: A prototype phase change memory storage array. In: HotStorage’11

  2. Are hybrid drives finally coming of age?—single-user. http://shop.objective-analysis.com/product.sc?productId=33

  3. Baker, M., Asami, S., Deprit, E., Ouseterhout, J., Seltzer, M.: Non-volatile memory for fast, reliable file systems. ACM SIGPLAN Not. 27(9), 10–22 (1992)

    Article  Google Scholar 

  4. Brunelle, A.D.: Blktrace user guide (2007)

  5. Bucy, J.S., Ganger, G.R.: Tech. rep. http://www.pdl.cmu.edu/DiskSim/

  6. Chen, S., Gibbons, P., Nath, S.: Rethinking database algorithms for phase change memory. CIDR11 pp. 21–31 (2011)

  7. Ding, X., Jiang, S., Chen, F., Davis, K., Zhang, X.: Diskseen: exploiting disk layout and access history to enhance i/o prefetch. In: USENIX ATC (2007)

  8. Doh, I., Choi, J., Lee, D., Noh, S.: Exploiting non-volatile ram to enhance flash file system performance. In: ACM EMSOFT’07

  9. Doh, I., Lee, H., Moon, Y., Kim, E., Choi, J., Lee, D., Noh, S.: Impact of nvram write cache for file system metadata on i/o performance in embedded systems. In: ACM SAC’09

  10. Fotakis, D., Pagh, R., Sanders, P., Spirakis, P.: Space efficient hash tables with worst case constant access time. STACS 2003, 271–282 (2003)

    MathSciNet  MATH  Google Scholar 

  11. Gill, B., Modha, D.: Wow: wise ordering for writes-combining spatial and temporal locality in non-volatile caches. In: USENIX FAST’05

  12. Ipek, E., Condit, J., Nightingale, E.B., Burger, D., Moscibroda, T.: Dynamically replicated memory: building reliable systems from nanoscale resistive memories. In: ASPLOS’10

  13. Jiang, S., Ding, X., Chen, F., Tan, E., Zhang, X.: Dulo: an effective buffer cache management scheme to exploit both temporal and spatial locality. In: USENIX FAST’05

  14. Jiang, S., Zhang, X.: LIRS: an efficient low inter-reference recency set replacement policy to improve buffer cache performance. ACM SIGMETRICS Perform. Eval. Rev. 30, 31–42 (2002)

    Article  Google Scholar 

  15. Kim, C.: LRFU: A spectrum of policies that subsumes the least recently used and least frequently used policies. IEEE Trans. Comput. 50(12), 1352–1361 (2001)

    Article  MathSciNet  MATH  Google Scholar 

  16. Lee, E., Bahn, H., Noh, S.H.: Unioning of the buffer cache and journaling layers with non-volatile memory. In: FAST, pp. 73–80. USENIX (2013)

  17. Lee, K., Doh, I., Choi, J., Lee, D., Noh, S.: Write-aware buffer cache management scheme for nonvolatile ram. In: Proceedings of Advances in Computer Science and Technology. ACTA Press (2007)

  18. Li, D., Vetter, J.S., Marin, G., McCurdy, C., Cira, C., Liu, Z., Yu, W.: Identifying opportunities for byte-addressable non-volatile memory in extreme-scale scientific applications. In: Parallel & Distributed Processing Symposium (IPDPS), 2012 IEEE 26th International, pp. 945–956. IEEE (2012)

  19. Liu, X., Schrack, G.: An algorithm for encoding and decoding the 3-d hilbert order. IEEE Trans. Image Process. 6(9), 1333–1337 (1997)

    Article  Google Scholar 

  20. Liu, Z., Wang, B., Carpenter, P., Li, D., Vetter, J.S., Yu, W.: PCM-based durable write cache for fast disk I/O. In: Modeling, Analysis & Simulation of Computer and Telecommunication Systems (MASCOTS), 2012 IEEE 20th International Symposium on, pp. 451–458. IEEE (2012)

  21. Liu, Z., Wang, B., Wang, T., Tian, Y., Xu, C., Wang, Y., Yu, W., Cruz, C.A., Zhou, S., Clune, T., et al.: Profiling and improving i/o performance of a large-scale climate scientific application. In: Computer Communications and Networks (ICCCN), 2013 22nd International Conference on, pp. 1–7. IEEE (2013)

  22. Micron phase change memory. http://www.micron.com/products/phase-change-memory

  23. Nightingale, T., Hu, Y., Yang, Q.: The design and implementation of a dcd device driver for unix. In: USENIX ATC’99

  24. O’neil, E., O’neil, P., Weikum, G.: The LRU-K page replacement algorithm for database disk buffering. In: ACM SIGMOD’93

  25. OSDL: Iometer project. http://www.iometer.org/ (2004)

  26. Pagh, R., Rodler, F.: Cuckoo hashing. AlgorithmsESA 2001, 121–133 (2001)

    MathSciNet  MATH  Google Scholar 

  27. Park, Y., Lim, S., Lee, C., Park, K.: Pffs: a scalable flash memory file system for the hybrid architecture of phase-change ram and nand flash. In: ACM SAC’08

  28. Qureshi, M., Karidis, J., Franceschini, M., Srinivasan, V., Lastras, L., Abali, B.: Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling. In: IEEE/ACM Micro’09

  29. Qureshi, M.K., Srinivasan, V., Rivers, J.A.: Scalable high performance main memory system using phase-change memory technology. In: Proc. of the Internationl Symposium on Computer Architecture (2009)

  30. Ramos, L., Gorbatov, E., Bianchini, R.: Page placement in hybrid memory systems. In: Proc. of the International Conference on Supercomputing (2011)

  31. Rosenblum, M., Ousterhout, J.: The design and implementation of a log-structured file system. ACM SIGOPS Oper. Syst. Rev. 25(5), 1–15 (1991)

    Article  Google Scholar 

  32. Seong, N.H., Woo, D.H., Lee, H.H.S.: Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. In: ISCA’10

  33. Shi, L., Li, J., Jason Xue, C., Zhou, X.: Hybrid nonvolatile disk cache for energy-efficient and high-performance systems. ACM Trans. Des. Autom. Electron. Syst. 18(1), 8 (2013)

    Google Scholar 

  34. SNIA BlockIO Traces. http://iotta.snia.org/tracetypes/3 (2006)

  35. Soundararajan, G., Prabhakaran, V., Balakrishnan, M., Wobber, T.: Extending ssd lifetimes with disk-based write caches. In: USENIX FAST’10

  36. Sun, G., Joo, Y., Chen, Y., Niu, D., Xie, Y., Chen, Y., Li, H.: A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. In: IEEE HPCA’10

  37. Umass trace repository. http://traces.cs.umass.edu/

  38. Wang, A., Reiher, P., Popek, G., Kuenning, G.: Conquest: Better performance through a disk/persistent-ram hybrid file system. In: USENIX ATC’02

  39. Wang, B., Liu, Z., Wang, X., Yu, W.: Eliminating intra-warp conflict misses in gpu. In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE). IEEE (2015)

  40. Wang, B., Wu, B., Li, D., Shen, X., Yu, W., Jiao, Y., Vetter, J.S.: Exploring hybrid memory for gpu energy efficiency through software-hardware co-design. In: Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, PACT ’13, pp. 93–102. IEEE Press, Piscataway, NJ, USA (2013)

  41. Wang, J., Dong, X., Xie, Y., Jouppi, N.P.: i2wap: Improving non-volatile cache lifetime by reducing inter-and intra-set write variations. In: High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th International Symposium on, pp. 234–245. IEEE (2013)

  42. Woodhouse, D.: Jffs: The journalling flash file system. In: Ottawa Linux Symposium, vol. 2001 (2001)

  43. Zhang, W., Li, T.: Exploring phase change memory and 3D die-stacking for power/thermal friendly, fast and durable memory architecture. In: International Conference on Parallel Architecture and Compilation Techniques (2009)

  44. Zhou, P., Zhao, B., Yang, J., Zhang, Y.: A durable and energy efficient main memory using phase change memory technology. In: ISCA’09

  45. Zhou, Y., Philbin, J., Li, K.: The multi-queue replacement algorithm for second level buffer caches. In: USENIX ATC’02

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Acknowledgements

We are thankful to Mr. Michael Pritchard for his comments on the paper. This work is supported in part by the NSF awards ACI-1561041, CNS-1320016 and CNS-1059376 and by a UT-Battelle Grant to Auburn University.

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Authors and Affiliations

  1. Auburn University, Auburn, AL, USA

    Zhuo Liu & Bin Wang

  2. Florida State University, Tallahassee, FL, USA

    Weikuan Yu

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  1. Zhuo Liu
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Correspondence to Weikuan Yu.

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Liu, Z., Wang, B. & Yu, W. HALO: a fast and durable disk write cache using phase change memory. Cluster Comput 21, 1275–1287 (2018). https://doi.org/10.1007/s10586-017-1076-0

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