Energy efficient parallel hybrid adder architecture for 3X generation in radix-8 booth encoding

Abstract

The need for hard (3X) multiple generation in radix-8 booth encoding increases the complexity of partial product generation and the latency of the multiplier. The source of delay is primarily the propagation of carry signals. A variety of carry propagate adder architectures have been studied to overcome this drawback. In this paper, we propose a hybrid adder architecture that precomputes the simultaneous generation of pseudo carry signals by exploiting the symmetry of 3X multiple and the final carry generation using Ling prefix network. As the Ling adder in the carry path reduces the complexity, the proposed adder results in significant improvement in the power delay product (${\sim }$25–55%) compared to state of the art 64 bit adders. This adder decreases the number of logic gates in the critical path, leading to a reduction in static power consumption. As a design metric, it is necessary to minimize the energy dissipation of logic modules, the results indicate that the proposed hybrid adder would fulfil the requirements of processors in deep sub-micron VLSI technology.