Low power NoC architecture based dynamic reconfigurable system

Abstract

The on chip communication intention is difficult due to communication necessities and the difficulty of the objective application is great. Notably, different communication areas might be actualized utilizing a similar chip range, for example, to enable various parallel applications to be stacked onto the device. So the system on chip (SoC) deployed in different topologies with different design parameters to achieve the requirements of the target application. Classical communication methods such as point to point, the bus is not an appropriate solution for future SoCs. That is difficult to send signals starting with one end then onto the next term of a clock cycle. Issues, for example, global wire delay and global synchronization will restrict us. With a specific end goal to beat these problems, architect utilizes new models, procedures, and tools from network design field and apply them to SoCs plan that prompts modern worldview called network on a chip. In this paper, the design components used and the operation of the proposed architecture is same with network on chip (NoC) approach. But it differs in the communication architecture with the introduction of the on-chip peripheral bus. And it differs from the NoC by its switching networks. We modified the switching system that is developed to support dynamically reconfigurable network. Due to this modification in the switching system restrict the area and the power use of the NoC.