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High performance decoding aware FPGA bit-stream compression using RG codes

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Abstract

FPGA design for complex applications need high capacity of configuration memory. To fullfil the large memory requirement, higher end FPGAs are required and it leads to higher cost. In order to reduce the cost constraint, bit-stream compression is prominently involved to reduce the bit-stream size and the memory requirement of FPGA configuration. In this paper new code compression techniques are proposed with minimum cost. The proposed code compression techniques RG-1 and RG-2 codes are designed based on the combination of run length and Golomb coding. The proposed RG codes overcome the limitation of both run length and Golomb coding techniques. The main contribution of this work is to analyze the proposed work in terms of number of 1’s, number of transitions and size of compressed bits. The comparison result shows that the RG code is more robust when compared to other traditional code compression techniques. The results shows that CR improvement of 9 and 5% compare with RLE for the RG-1 and RG-2 respectively and CR improvement of 7 and 2% compare with golomb for the RG-1 and RG-2 respectively.

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Authors and Affiliations

  1. Hindusthan College of Engineering and Technology, Coimbatore, India

    J. Satheesh Kumar

  2. Tamil Nadu College of Engineering, Coimbatore, India

    G. Saravana Kumar

  3. GCT, Coimbatore, India

    A. Ahilan

Authors
  1. J. Satheesh Kumar
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  2. G. Saravana Kumar
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  3. A. Ahilan
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Correspondence to J. Satheesh Kumar.

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Satheesh Kumar, J., Saravana Kumar, G. & Ahilan, A. High performance decoding aware FPGA bit-stream compression using RG codes. Cluster Comput 22 (Suppl 6), 15007–15013 (2019). https://doi.org/10.1007/s10586-018-2486-3

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  • DOI: https://doi.org/10.1007/s10586-018-2486-3

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