Skip to main content
SpringerLink
Log in

Customized simulated annealing based decision algorithms for combinatorial optimization in VLSI floorplanning problem

  • Published:
Computational Optimization and Applications Aims and scope Submit manuscript

Abstract

Modern very large scale integration technology is based on fixed-outline floorplan constraints, mostly with an objective of minimizing area and wirelength between the modules. The aim of this work is to minimize the unused area, that is, dead space in the floorplan, in addition to these objectives. In this work, a Simulated Annealing Algorithm (SAA) based heuristic, namely Simulated Spheroidizing Annealing Algorithm (SSAA) has been developed and improvements in the proposed heuristic algorithm is also suggested to improve its performance. Exploration capability of the proposed algorithm is due to the mechanism of reducing the uphill moves made during the initial stage of the algorithm, extended search at each temperature and the improved neighborhood search procedure. The proposed algorithm has been tested using two kinds of benchmarks: Microelectronics Center of North Carolina (MCNC) and Gigascale Systems Research Center (GSRC). The performance of the proposed algorithm is compared with that of other stochastic algorithms reported in the literature and is found to be efficient in producing floorplans with very minimal dead space. The proposed SSAA algorithm is also found more efficient for problems of larger sizes.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10

Similar content being viewed by others

References

  1. Adya, S.N., Markov, I.L.: Fixed—outline floorplanning: enabling hierarchical design. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 11(6), 1120–1135 (2003)

    Article  Google Scholar 

  2. Adya, S.N., Markov, I.L.: Fixed-outline floorplanning through better local search. In: ICCD ’01: Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors, pp. 328–334. IEEE Computer Society, Austin (2001)

    Google Scholar 

  3. Alpert, C.J., Mehta, D.P., Sapatnekar, S.S.: Handbook of Algorithms for Physical Design Automation, 1st edn. Auerbach, Boston (2008)

    Book  Google Scholar 

  4. Chen, G., Guo, W., Chen, Y.: A PSO-based intelligent decision algorithm for VLSI floorplanning. Soft Comput., Fusion Found. Methodol. Appl. 14(12), 1329–1337 (2010). doi:10.1007/s00500-009-0501-6

    Google Scholar 

  5. Chen, T.C., Chang, Y.W.: Modern floorplanning based on B*-tree and fast simulated annealing. IEEE Trans. CAD 25(4), 510–522 (2006)

    Google Scholar 

  6. Fang, J.P., Chang, Y.L., Chen, C.C., Liang, W.Y., Hsieh, T.J., Satria, M., Han, C.C.: A parallel simulated annealing approach for floorplanning in VLSI. In: Algorithms and Architectures for Parallel Processing. Lecture Notes in Computer Science, vol. 5574, pp. 291–302. Springer, Berlin/Heidelberg (2009)

    Chapter  Google Scholar 

  7. Guo, P.N., Cheng, C.K., Yoshimura, T.: An O-tree representation of non-slicing floorplan and its applications. In: DAC ’99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference, pp. 268–273. ACM, New York (1999). doi:10.1145/309847.309928

    Chapter  Google Scholar 

  8. Hong, X., Huang, G., Cai, Y., Gu, J., Dong, S., Cheng, C.K., Gu, J.: Corner block list: an effective and efficient topological representation of non-slicing floorplan. In: Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, ICCAD ’00, pp. 8–12. IEEE Press, Piscataway (2000). URL: http://portal.acm.org/citation.cfm?id=602902.602905

    Google Scholar 

  9. Kahng, A.B.: Classical floorplanning harmful. In: ISPD ’00: Proceedings of the 2000 International Symposium on Physical Design, pp. 207–213. ACM, New York (2000). doi:10.1145/332357.332401

    Chapter  Google Scholar 

  10. Kang, M., Dai, W.: General floorplanning with L-shaped, T-shaped and soft blocks based on bounded slicing grid structure. In: Proceedings of Asia and South Pacific -Design Automation Conference, pp. 265–270 (1997)

    Google Scholar 

  11. Kang, M., Dai, W.: Arbitrary rectilinear block packing based on sequence pair. In: Proceedings IEEE/ACM International Conference on Computer Aided Desingn (ICCAD), pp. 259–266 (1998)

    Google Scholar 

  12. Kirpatrick, S., Gelatt, C., Vecchi, M.: Optimization by simulated annealing. Science 220(4598), 671–680 (1983)

    Article  MathSciNet  Google Scholar 

  13. Lin, C.T., Chen, D.S., Wang, Y.W.: Robust fixed-outline floorplanning through evolutionary search. In: ASP-DAC ’04: Proceedings of the 2004 Asia and South Pacific Design Automation Conference, pp. 42–44. IEEE Press, Piscataway (2004)

    Google Scholar 

  14. Lin, J.M., Chang, Y.W.: TCG: A transitive closure graph-based representation for non-slicing floorplans. In: Proceedings of the 38th Conference on Design Automation, Las Vegas, Nevada, pp. 764–769 (2001)

    Google Scholar 

  15. Lin, J.M., Chang, Y.W., Lin, S.P.: Corner sequence-A P-admissible floorplan representation with a worst case linear-time packing scheme. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 11(4), 679–686 (2003)

    Article  Google Scholar 

  16. Murata, H., Fujiyoshi, K., Kaneko, M.: VLSI/PCB placement with obstacles based on sequence-pair. In: ISPD ’97: Proceedings of the 1997 International Symposium on Physical Design, pp. 26–31. ACM, New York (1997). doi:10.1145/267665.267675

    Chapter  Google Scholar 

  17. Murata, H., Fujiyoshi, K., Nakatake, S., Kajitani, Y.: Rectangle-packing-based module placement. In: ICCAD ’95: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, pp. 472–479. IEEE Computer Society, Washington (1995)

    Google Scholar 

  18. Murata, H., Kuh, E.S.: Sequence-pair based placement method for hard/soft/pre-placed modules. In: ISPD ’98: Proceedings of the 1998 International Symposium on Physical Design, pp. 167–172. ACM, New York (1998). doi:10.1145/274535.274560

    Chapter  Google Scholar 

  19. Nakatake, S., Fujiyoshi, K., Murata, H., Kajitani, Y.: Module placement on BSG-structure and IC layout applications. In: ICCAD ’96: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, pp. 484–491. IEEE Computer Society, Washington (1996)

    Google Scholar 

  20. Nakatake, S., Fujiyoshi, K., Murata, H., Kajitani, Y.: Module placement on BSG-structure with pre-places modules and rectilinear modules. In: Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC ’98), pp. 433–439 (1998)

    Google Scholar 

  21. OpenMP. URL: http://www.openmp.org/blog/

  22. Otten, R.H.: Automatic floorplan design. In: DAC ’82: Proceedings of the 19th Design Automation Conference, pp. 261–267. IEEE Press, Piscataway (1982)

    Google Scholar 

  23. Pang, Y., Cheng, C.K., Yoshimura, T.: An enhanced perturbing algorithm for floorplan design using the o-tree representation. In: ISPD ’00: Proceedings of the 2000 International Symposium on Physical Design, pp. 168–173. ACM, New York (2000). doi:10.1145/332357.332395

    Chapter  Google Scholar 

  24. Sechen, C.: Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing. In: DAC ’88: Proceedings of the 25th ACM/IEEE Design Automation Conference, pp. 73–80. IEEE Computer Society Press, Los Alamitos (1988)

    Google Scholar 

  25. Sechen, C., Sangiovanni-Vincentelli, A.: The timberwolf placement and routing package. IEEE J. Solid-State Circuits 20(2), 510–522 (1985)

    Article  Google Scholar 

  26. Sechen, C., Sangiovanni-Vincentelli, A.: Timberwolf3.2: a new standard cell placement and global routing package. In: DAC ’86: Proceedings of the 23rd ACM/IEEE Design Automation Conference, pp. 432–439. IEEE Press, Piscataway (1986)

    Google Scholar 

  27. Tang, M., Sebastian, A.: A genetic algorithm for VLSI floorplanning using O-tree representation. In: Applications on Evolutionary Computing. Lecture Notes in Computer Science, vol. 3449, pp. 215–224. Springer, Berlin/Heidelberg (2005)

    Chapter  Google Scholar 

  28. Tang, M., Yao, X.: A memetic algorithm for VLSI floorplanning. IEEE Trans. Syst. Man Cybern. 37(1), 62–69 (2007)

    Article  Google Scholar 

  29. Tang, X., Wong, D.F.: FAST-SP: a fast algorithm for block placement based on sequence pair. In: Proceedings of the 2001 Asia and South Pacific Design Automation Conference, ASP-DAC ’01, pp. 521–526. ACM, New York (2001). doi:10.1145/370155.370523

    Chapter  Google Scholar 

  30. Wang, T.C., Wong, D.F.: An optimal algorithm for floorplan area optimization. In: DAC ’90: Proceedings of the 27th ACM/IEEE Design Automation Conference, pp. 180–186. ACM, New York (1990). doi:10.1145/123186.123253

    Chapter  Google Scholar 

  31. Wong, D.F., Leong, H.W., Liu, C.L.: Simulated Annealing for VLSI Design. Kluwer Academic, Norwell (1988)

    Book  MATH  Google Scholar 

  32. Wong, D.F., Liu, C.L.: A new algorithm for floorplan design. In: DAC ’86: Proceedings of the 23rd ACM/IEEE Design Automation Conference, pp. 101–107. IEEE Press, Piscataway (1986)

    Google Scholar 

  33. Wu, G.M., Wu, S.W., Chang, Y.W., Chang, Y.C.: B*-trees: A new representation for non-slicing floorplans. In: Proceedings of the 37th Design Automation Conference, pp. 458–463 (2000). doi:10.1109/DAC.2000.855354

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. National Centre for Advanced Research in Discrete Mathematics (n-CARDMATH), Kalasalingam University, Anand Nagar, Krishnankoil, 626126, Tamil Nadu, India

    S. Anand

  2. Department of Mechanical Engineering, Kalasalingam University, Anand Nagar, Krishnankoil, 626126, Tamil Nadu, India

    S. Saravanasankar

  3. Department of Electronics and Communication Engineering, Kalasalingam University, Anand Nagar, Krishnankoil, 626126, Tamil Nadu, India

    P. Subbaraj

Authors
  1. S. Anand
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. S. Saravanasankar
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. P. Subbaraj
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to S. Anand.

Additional information

The authors thank the Department of Science and Technology, New Delhi, Government of India, for the support under project no: SR/S4/MS: 326/06.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Anand, S., Saravanasankar, S. & Subbaraj, P. Customized simulated annealing based decision algorithms for combinatorial optimization in VLSI floorplanning problem. Comput Optim Appl 52, 667–689 (2012). https://doi.org/10.1007/s10589-011-9442-y

Download citation

  • Received:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10589-011-9442-y

Keywords

Search

Navigation