Skip to main content
SpringerLink
Log in

ARTS: A SystemC-based framework for multiprocessor Systems-on-Chip modelling

  • Published:
Design Automation for Embedded Systems Aims and scope Submit manuscript

Abstract

One of the challenges of designing a heterogeneous multiprocessor SoC is to find the right partitioning of the application for the target platform architecture. The right partitioning is dependent on the characteristics of the processors and the network connecting them as well as the application. We present an abstract system-level modelling and simulation framework (ARTS) which allows for cross-layer modelling and analysis covering the application layer, middleware layer, and hardware layer. ARTS allows MPSoC designers to explore and analyze the network performance under different traffic and load conditions, consequences of different task mappings to processors (software or hardware) including memory and power usage, and effects of RTOS selection, including scheduling, synchronization and resource allocation policies.

We present the application and platform models of ARTS as well as their implementation in SystemC. We present the usage of the ARTS framework as seen from platform developers’ point of view, where new components may be created and integrated into the framework, and from application designers’ point of view, where existing components are used to explore possible implementations. The latter is illustrated through a case study of a real-time, smart phone application consisting of 5 applications with a total of 114 tasks mapped onto different platforms. Finally, we discuss the simulation performance of the ARTS framework in relation to scalability.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. The real-time operating system for multiprocessor systems. http://www.rtems.com, http://www.rtems.com

  2. Benini L, Bertozzi D, Bruni D, Drago N, Fummi F, Poncino M (2003) SystemC cosimulation and emulation of multiprocessor SoC designs. IEEE Computer 36(4):53–59

    Article  Google Scholar 

  3. Cai L, Gajski D (2003) Transaction-level modeling in system level design. CECS technical report (03-10), Center for Embedded Computer Systems, Information and Computer Science, University of California, Irvine, March 2003

  4. Cassidy AS, Paul JM, Thomas DE (2003) Layered, multi-threaded, high-level performance design. In: Proceedings of design automation & test in Europe conference (DATE 2003), March 2003, IEEE Computer Society, pp 954–959

  5. Dally WJ (1992) Virtual-channel flow control. IEEE Trans Parallel Distrib Syst 3(2):194–205

    Article  Google Scholar 

  6. Desment D, Verkest D, Man HD (2000) Operating system-based software generation for Systems-on-Chip. In: Design automation conference, DAC, June 2000

  7. Fummi F, Gallo P, Martini S, Perbellini G, Poncino M, Ricciato F (2003) A timing-accurate modeling and simulation environment for networked embedded systems. In: Proceedings of the 42th design automation conference (DAC’03), June 2003, pp 42–47

  8. Fummi F, Martini S, Perbellini G, Poncino M, Ricciato F, Turolla M (2004) Heterogeneous co-simulation of networked embedded systems. In: Proceedings of the design, automation and test in Europe conference (DATE’04). IEEE, Febuary 2004

  9. Gerstlauer A, Yu H, Gajski D (2003) RTOS modelling for system-level design. In: Proceedings of the design automation & test in Europe conference (DATE 2003), March 2003, pp 132–137

  10. Gerstlauer A, Yu H, Gajski DD (2003) RTOS modeling for system-level design. In: Proceedings of the design, automation and test in Europe conference (DATE’03). March 2003, IEEE Computer Society, pp 130–135

  11. Grötker T, Liao S, Martin G, Swan S (2002) System design with SystemC. Kluwer Academic, Dordrecht

    Google Scholar 

  12. Haverinen A, Leclercq M, Weyrich N, Wingard D (2002) SystemC based SoC communication modeling for the OCP protocol. White paper (downloadable from http://www.ocpip.org), OCP-IP Association/Nokia, Texas Instruments, Synopsys, Sonics, October 2002

  13. Hessel F, Rosa VM, Reis IM, Planner R, Marcon CAM, Susin AA (2004) Abstract RTOS modeling for embedded systems. In: IEEE international workshop on rapid system prototyping

  14. Honda S, Wakabayashi T, Tomiyama H, Takada H (2004) RTOS-centric hardware/software cosimulator for embedded system design. In: Second IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis (CODES/ISSS’04), September 2004

  15. Knudsen P, Madsen J (1999) Integrating communication protocol selection with hardware/software codesign. IEEE Trans Comput-Aided Des Integr Circuits Syst 18(8):1077–1095

    Article  Google Scholar 

  16. Loghi M, Angiolini F, Bertozzi D, Benini L, Zafalon R (2004) Analyzing on-chip communication in an MPSoC environment. In: Proceedings of the design, automation and test in Europe conference (DATE’04). IEEE, February 2004, pp 752–757

  17. Madsen J, Mahadevan S, Virk K, Gonzalez M (2003) Network-on-chip modeling for system-level multiprocessor simulation. In: Proceedings of the IEEE real-time systems symposium (RTSS 2003), December 2003

  18. Madsen J, Virk K, Gonzalez M (2003) Abstract RTOS modelling for multiprocessor System-on-Chip. In: Proceedings of the international symposium on System-On-Chip, November 2003

  19. Mahadevan S, Storgaard M, Madsen J, Virk K (2005) ARTS: A system-level framework for modeling MPSoC components and analysis of their causality. In: The 13th IEEE international symposium on modeling, analysis, and simulation of computer and telecommunication systems (MASCOTS’05). September 2005, IEEE Computer Society

  20. Moigne RL, Pasquier O, Calvez J-P (2004) A generic RTOS model for real-time systems simulation with SystemC. In: Proceedings of the design, automation and test in Europe conference (DATE’04). IEEE Computer Society, p 30082

  21. Ogawa O, de Noyer SB, Chauvet P, Shinohara K, Watanabe Y, Niizuma H, Sasaki T, Takai Y (2003) A practical approach for bus architecture optimization at transaction level. In: Proceedings of the design, automation and test in Europe conference (DATE’03), March 2003. IEEE

  22. Pasricha S, Dutt N, Ben-Romdhane M (2004) Extending the transaction level modeling approach for fast communication architecture exploration. In: Proceedings of the 38th design automation conference (DAC’04), ACM, pp 113–118

  23. Posadas H, Ádamez J, Sánchez P, Villar E, Blasco F (2006) POSIX modeling in SystemC. In: ASP-DAC, pp 485–490

  24. Schmitz MT, Al-Hashimi BM, Eles P (2004) System-level design techniques for energy-efficient embedded systems. Kluwer Academic, Dordercht

    MATH  Google Scholar 

  25. Sha L, Rajkumar R, Lehoczky JP (1990) Priority-inheritance protocols: An approach to real-time synchronization. IEEE Trans Comput 39:1175–1185

    Article  MathSciNet  Google Scholar 

  26. Sifakis J (2001) Modeling real-time systems—challenges and work directions. In: EMSOFT, Lecture notes in computer science, vol 2211, pp 373–389

  27. Stankovic A, Wang H, Humphrey M, Zhu R, Poornalingam R, Lu C (2001) VEST: Virginia embedded systems toolkit. In: Proceedings of the real-time embedded systems workshop, December 2001, pp 132–137

  28. Sun J, Liu J (1996) Synchronization protocols in distributed real-time systems, In: Proceedings of the 16th international conference on distributed computing systems, May 1996. IEEE Computer Society, pp 38–45

  29. Tomiyama H, Cao Y, Murakami K (2001) Modeling fixed-priority preemptive multi-task systems in SpecC. In: SASIMI, October 2001

Download references

Author information

Authors and Affiliations

  1. Computer Science & Engineering Section, Informatics & Mathematical Modeling, Technical University of Denmark, Lyngby, Denmark

    Shankar Mahadevan, Kashif Virk & Jan Madsen

Authors
  1. Shankar Mahadevan
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Kashif Virk
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Jan Madsen
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Shankar Mahadevan.

Additional information

This work has been partially funded by ARTIST2 (IST-004527).

Rights and permissions

Reprints and permissions

About this article

Cite this article

Mahadevan, S., Virk, K. & Madsen, J. ARTS: A SystemC-based framework for multiprocessor Systems-on-Chip modelling. Des Autom Embed Syst 11, 285–311 (2007). https://doi.org/10.1007/s10617-007-9007-6

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10617-007-9007-6

Keywords

Search

Navigation