Rethinking the synthesis of buses, data mapping, and memory allocation for MPSoC

Abstract

Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the target applications, these systems will also have custom memory and bus architectures. Because of performance and cost constraints, these systems must be carefully designed to balance system partitioning and resource sharing. The sheer size of the design space requires that tools be able to do this balancing. We have developed an augmented simulated annealing synthesis tool that uses system performance and layout evaluation to drive simultaneous data mapping, memory allocation and bus synthesis. Exploring these optimizations at the same time, our approach reverses traditional techniques and determines bus topology first rather than last, thereby exposing a larger design space and taking advantage of cost-saving resource sharing unavailable to previous approaches that allocate memories first. This results in 20% cost reduction for high-performance designs as well as 27% for low-cost designs in comparison with an approach that performs memory allocation and data mapping separately from bus synthesis.