Abstract
In High-Level Synthesis, Binary Synthesis is a method for synthesizing compiled applications for which the source code is not available. One of the advantages of FPGAs over processors is the availability of multiple internal and external memory banks. Binary synthesis tools use multiple memory banks if they are able to recover data-structures from the binary. In this work we improve the recovery of data-structures by introducing dynamic memory analysis and combining it with improved static memory analysis. We show that many applications can only be synthesized using dynamic memory analysis. We present two FPGA based architectures for implementing the bound-checking and recovery for the synthesized code. Our experiments show that the proposed technique accelerates the execution of applications which use multiple memory banks concurrently. We demonstrate that many binary applications indeed benefit from this technique.
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References
Devadas S, Ghosh A, Keutzer K (1994) Logic synthesis. McGraw-Hill, New York
Stitt G, Vahid F (2007) Binary synthesis. ACM Trans Des Autom Electron Syst 12(3):1–30
Hookway RJ, Herdeg MA (1997) Digital fx!32: combining emulation and binary translation. Digit Tech J 9:3–12
Howard DL, Lipasti MH (1999) The effect of program optimization on trace cache efficiency. In: IEEE PACT, pp 256–261. [Online]. Available: citeseer.ist.psu.edu/244939.html
Muth R, Debray S, Watterson S, de Bosschere K (1998) alto: A link-time optimizer for the DEC alpha. Tech Rep TR98-14, Wednesday, 9 1998. [Online]. Available: citeseer.ist.psu.edu/muth98alto.html
Weide BW, Heym WD, Hollingsworth JE (1994) Reverse engineering of legacy code is intractable. Columbus, Ohio, Tech Rep OSU-CISRC-10/94-TR55, Oct 1994. [Online]. Available: citeseer.ist.psu.edu/weide94reverse.html
Kruegel C, Robertson W, Valeur F, Vigna G (2004) Static disassembly of obfuscated binaries. [Online]. Available: citeseer.ist.psu.edu/kruegel04static.html
Zaretsky D, Mittal G, Tang X, Banerjee P (2004) Overview of the freedom compiler for mapping dsp software to fpgas. In: FCCM ’04: proceedings of the 12th annual IEEE symposium on field-programmable custom computing machines. IEEE Computer Society, Washington, pp 37–46
Lysecky R, Vahid F, Tan SX-D (2004) Dynamic fpga routing for just-in-time fpga compilation. In: DAC ’04: proceedings of the 41st annual design automation conference. ACM, New York, pp 954–959
Stitt G, Lysecky R, Vahid F (2003) Dynamic hardware/software partitioning: a first approach. In: DAC ’03: proceedings of the 40th annual design automation conference. ACM, New York, pp 250–255
Lysecky R, Vahid F (2005) A study of the speedups and competitiveness of fpga soft processor cores using dynamic hardware/software partitioning. In: DATE ’05: proceedings of the conference on design, automation and test in Europe. IEEE Computer Society, Washington, pp 18–23
Stitt G, Guo Z, Vahid F, Najjar W (2005) Techniques for synthesizing binaries to an advanced register/memory structure. In: FPGA 05: proceedings of the 2005 ACM/SIGDA 13th international symposium on field-programmable gate arrays. ACM, New York, pp 118–124
Guo Z, Buyukkurt B, Najjar W (2004) Input data reuse in compiling window operations onto reconfigurable hardware. In: Proceedings of the ACM symposium on languages, compilers and tools for embedded systems (LCTES). ACM, New York, pp 249–256
Guo Z, Najjar W, Buyukkurt B (2008) Efficient hardware code generation for fpgas. ACM Trans Archit Code Optim, 5(1):1–26
Ben-Asher Y, Rotem N (2008) Synthesis for variable pipelined function units. In: International symposium on system-on-chip, SOC 2008. IEEE Computer Society, New York, pp 1–4
C. to Verilog, http://c-to-verilog.com
Nethercote N, Seward J (2007) Valgrind: a framework for heavyweight dynamic binary instrumentation. ACM SIGPLAN Not 42(6):89–100
Nethercote N, Seward J (2003) Valgrind: a program supervision framework. Electron Notes Theor Comput Sci 89(2):44–66
Marathe J, Mueller F, Mohan T, Mckee SA, Supinski BRD, Yoo A (2007) Metric: memory tracing via dynamic binary rewriting to identify cache inefficiencies. ACM Trans Program Lang Syst 29
Zhang X, Gupta R (2005) Whole execution traces and their applications. ACM Trans Archit Code Optim 2:301–334
Gerlek MP, Stoltz E, Wolfe M (1995) Beyond induction variables: detecting and classifying sequences using a demand-driven ssa form. ACM Trans Program Lang Syst 17:85–122
Lattner C, Adve V (2004) LLVM: a compilation framework for lifelong program analysis & transformation. In: Proceedings of the international symposium on code generation and optimization (CGO’04), Palo Alto, California, Mar 2004. [Online]. Available: citeseer.ist.psu.edu/lattner04llvm.html
Housel BC, Halstead MH (1974) A methodology for machine language decompilation. In: ACM 74: proceedings of the 1974 annual conference. ACM, New York, pp 254–260
Bermudo N, Krall A, Horspool N (2005) Control flow graph reconstruction for assembly language programs with delayed instructions. In: SCAM ’05: proceedings of the fifth IEEE international workshop on source code analysis and manipulation. IEEE Computer Society, Washington, pp 107–118
Adve V, Lattner C, Brukman M, Shukla A, Gaeke B (2003) Llva: A low-level virtual instruction set architecture. [Online]. Available: citeseer.ist.psu.edu/article/adve03llva.html
Dabah G (2005) Distorm, the disassembly library. http://ragestorm.net/distorm/
Cifuentes C, Gough KJ (1994) Decompilation of binary programs. Tech. Rep. FIT-TR-1994-03, 19. [Online]. Available: citeseer.ist.psu.edu/cifuentes95decompilation.html
Wroblewski G (2002) General method of program code obfuscation. [Online]. Available: citeseer.ist.psu.edu/wroblewski02general.html
Kral S, Franchetti F, Lorenz J, Ueberhuber C. Simd vectorization of straight line code. [Online]. Available: citeseer.ist.psu.edu/kral03simd.html
Schleef D. Library for optimized inner loops. http://liboil.freedesktop.org/wiki
Rau BR (1994) Iterative modulo scheduling: an algorithm for software pipelining loops. In: Proceedings of the 27th annual international symposium on microarchitecture, pp 63–74
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Rotem, N., Asher, Y.B. Combining static and dynamic array detection for binary synthesis with multiple memory ports. Des Autom Embed Syst 15, 1–18 (2011). https://doi.org/10.1007/s10617-010-9065-z
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DOI: https://doi.org/10.1007/s10617-010-9065-z