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Probability-based static wear-leveling algorithm for block and hybrid-mapping NAND flash memory

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Abstract

Owing to its desirable characteristics, flash memory has become attractive to different hardware vendors as a primary choice for data storage. However, because of a limited number of block-erase lifecycles, it has become mandatory to redesign the existing approaches to maximize the flash memory lifetime. Wear-leveling is a mechanism that helps to evenly distribute erase operations to all blocks and enhance lifetime. This research proposes probability-based static wear-leveling. Based on the Markov Chain theory, the future state depends on the present state. Mapping is implemented according to the present visit probability of each logical block in the next state. In each state, the wear-leveling distribution is computed using the standard deviation to determine whether it exceeds the threshold. If it does exceed the threshold, wear-leveling is maintained throughout all blocks in the flash memory by swapping the hot blocks with cold blocks. Using real system-based traces, we have proved that our proposal outperforms the existing design in terms of wear-leveling.

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References

  1. NXP Philips Semiconductors (2004) P89V51RD2 data sheet, March 2004

  2. http://en.wikipedia.org/wiki/Flash_memory

  3. Kwon SJ, Ranjitkar A, Ko YB, Chung TS (2011) FTL algorithm for NAND-type flash memories. Des Autom Embed Syst 15:191–224

    Article  Google Scholar 

  4. Toshiba America Electronic Components Flash Memory Fact Sheet, Inc (2007) NAND vs NOR flash memory technology overview

  5. Samsung Electronics (2007) NAND flash memory & Smartmedia Data Book

  6. Ban A (1999) Flash file system optimized for page-mode flash technologies. US Patent 5,937,425, 1999

  7. Ban A (1995) Flash file system. US Patent 5,404,485, 1995

  8. Estakhri P, Iman B (1999) Moving sequential sectors within a block of information in a flash memory mass storage architecture. US Patent 5,930,815, 1999

    Google Scholar 

  9. Kim J, Kim JM, Noh SH, Min SL, Cho Y (2002) A space efficient flash translation layer for compact flash systems. IEEE Trans Consum Electron 48:366–375

    Article  Google Scholar 

  10. Shinohara T (1999) Flash memory card with block memory address arrangement. US Patent 5,905,993, 1999

  11. Kim BS, Lee GY (2002) Method of driving remapping in flash memory and flash memory architecture suitable therefore. US Patent 6,381,176, 2002

    Google Scholar 

  12. Samsung Electronics (2010) NAND flash memory. K9F1G16U0M data book

  13. Samsung Electronics (2010) NAND flash memory. K9GAG08U0M data book

  14. Chung TS, Park DJ, Park S, Lee DH, Lee SW, Song HJ (2009) A survey of flash translation layer. J Syst Archit 55:332–343

    Article  Google Scholar 

  15. Micron Technology, Inc (2008) Wear-leveling techniques in NAND flash devices. Technical note TN-2 9-42

  16. Chang LP, Kuo TW (2002) An adaptive striping architecture for flash memory storage systems of embedded systems. In: IEEE real-time and embedded technology and applications symposium, pp 187–196

    Google Scholar 

  17. Chang LP (2007) On efficient wear-leveling for large-scale flash-memory storage systems. In: Proceeding of ACM symposium applied computing, pp 1126–1130

    Google Scholar 

  18. Gal E, Toledo S (2005) Algorithms and data structures for flash memories. ACM Comput Surv 37:138–163

    Article  Google Scholar 

  19. Teshome S, Chung TS (2011) A tri-pool dynamic wear-leveling algorithm for large scale flash memory storage systems. In: International conference on information science and applications, pp 1–6

    Google Scholar 

  20. Ban A, Hasbaron R (2004) Wear-leveling of static areas in flash memory. US Patent 6,732,221, May 2004, M-Systems

  21. Chang YH, Hsieh JW, Kuo TW (2010) Improving flash wear-leveling by proactively moving static data. IEEE Trans Comput 59:53–65

    Article  MathSciNet  Google Scholar 

  22. Chang LP, Huang LC (2011) A low-cost wear-leveling algorithm for block-mapping solid-state disks. ACM SIGPLAN Not 46:31–40

    Article  Google Scholar 

  23. Kim J, Kim JM, Noh SH, Min SL, Cho Y (2002) A space-efficient flash translation layer for compact flash systems. IEEE Trans Consum Electron 48:366–375

    Article  Google Scholar 

  24. Lee SW, Park DJ, Chung TS, Lee DH, Park S, Song HJ (2007) A log buffer-based flash translation layer using fully-associative sector translation. ACM Trans Embed Comput Syst. doi:10.1145/1275986.1275990

  25. Ross SM (2010) Introduction to probability models, 10th edn. Elsevier, San Diego, pp 191–290

    Book  MATH  Google Scholar 

  26. Shim G, Park YW, Park KH, Park KH (2011) A hybrid flash translation layer with adaptive merge for SSDs. ACM Trans Storage 6:15:1–15:27

    Article  Google Scholar 

  27. Wear_Leveling_AN (2010) Spansion Application Note (AN02). June 15, 2010

Download references

Acknowledgements

This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education Science and Technology (2010-0013487).

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Authors and Affiliations

  1. Department of Computer Engineering, Ajou University, Suwon, Republic of Korea

    Yared Hailu Gudeta, Se Jin Kwon & Tae-Sun Chung

  2. Department of Computer Science and Engineering, Chungnam National University, Daejeon, Republic of Korea

    Eun-Sun Cho

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  1. Yared Hailu Gudeta
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  2. Se Jin Kwon
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  3. Eun-Sun Cho
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  4. Tae-Sun Chung
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Correspondence to Tae-Sun Chung.

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Gudeta, Y.H., Kwon, S.J., Cho, ES. et al. Probability-based static wear-leveling algorithm for block and hybrid-mapping NAND flash memory. Des Autom Embed Syst 16, 241–264 (2012). https://doi.org/10.1007/s10617-013-9108-3

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  • DOI: https://doi.org/10.1007/s10617-013-9108-3

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