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Recent trends in embedded system software performance estimation

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Abstract

It is observed that due to the availability of fast and highly efficient processors, many embedded system developers are attracted to implement the majority of the system components in software rather than hardware. Software implementation offers a great level of flexibility and scalability of the design. At the same time, a wide choice exists between generic processors, DSP processors, network processors, etc. This increases the design space exploration by many folds to select an appropriate processor or a processor version for a specific application or application component. In this review, recent prominent directions for embedded software performance estimation have been discussed and their salient features are summarized.

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References

  1. Wang Z, Henkel J (2012) Accurate source-level simulation of embedded software with respect to compiler optimizations. In: Conference and exhibition on design, automation and test in Europe (DATE), pp 382–387. doi:10.1109/DATE.2012.6176501

    Google Scholar 

  2. Lattuda M, Ferrandi F (2012) Performance estimation of embedded software with confidence levels. In: 17th Asia and South Pacific design automation conference (ASP-DAC), pp 573–578. doi:10.1109/ASPDAC.2012.6165022

    Chapter  Google Scholar 

  3. Wang Z, Lu K, Herkersdorf A (2011) An approach to improve accuracy of source-level TLMs of embedded software. In: Conference and exhibition on design, automation & test in Europe conference & exhibition (DATE), pp 1–6. doi:10.1109/DATE.2011.5763045

    Google Scholar 

  4. Patel R, Rajawat A (2011) A survey of embedded software profiling methodologies. Int J Embed Syst Appl 1(2):19–40. doi:10.5121/ijesa.2011.1203

    Google Scholar 

  5. Stattelmann S, Bringmann O, Rosenstiel W (2011) Fast and accurate source-level simulation of software timing considering complex code optimizations. In: 48th ACM/EDAC/IEEE design automation conference (DAC), pp 486–491

    Google Scholar 

  6. Lattuda M, Ferrandi F (2010) Performance modeling of embedded applications with zero architectural knowledge. In: IEEE/ACM/IFIP conference on Hardware/Software codesign and system synthesis (CODES+ISSS), pp 277–286. doi:http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5751512&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5751512

    Google Scholar 

  7. Lattuda M, Ferrandi F (2010) Combining target-independent analysis with dynamic profiling to build the performance model of a DSP. In: 10th IEEE international conference on computer and information technology (CIT), pp 1895–1901. doi:10.1109/CIT.2010.324

    Google Scholar 

  8. Wang Z, Herkersdorf A (2010) Software performance simulation strategies for high-level embedded system design. Int J Perform Evol 67(8):717–739. doi:10.1016/j.peva.2009.07.003

    Article  Google Scholar 

  9. Ray A, Srikanthan T, Jigang W (2010) Rapid techniques for performance estimation of processors. J Res Pract Inf Technol 42(2):147–165

    Google Scholar 

  10. Wang Z, Herkersdorf A (2009) An efficient approach for system-level timing simulation of compiler-optimized embedded software. In: 46th ACM/IEEE design automation conference (DAC), pp 220–225

    Google Scholar 

  11. Ferrandi F, Lattuada M, Pilato C, Tumeo A (2009) Performance estimation for task graphs combining sequential path profiling and control dependence regions. In: 7th IEEE/ACM international conference on formal methods and models for co-design (MEMOCODE ’09), pp 131–140

    Chapter  Google Scholar 

  12. Bouchhima A, Gerin P, Petrot F (2009) Automatic instrumentation of embedded software for high level hardware/software co-simulation. In: Asia and South Pacific design automation conference (ASP-DAC), pp 546–551. doi:10.1109/ASPDAC.2009.4796537

    Google Scholar 

  13. Wang Z, Sanchez A, Herkersdorf A, Stechele W (2008) Fast and accurate software performance estimation during high-level embedded system design. In: EDA workshop, Hannover, Deutschland. doi:http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.120.3250

    Google Scholar 

  14. Oyamada M, Zschornack F, Wagner F (2008) Applying neural networks to performance estimation of embedded software. J Syst Archit 54:224–240. doi:10.1016/j.sysarc.2007.06.005

    Article  Google Scholar 

  15. Meyerowitz T, Sauermann M, Langen D, Sangiovanni-Vincentelli A (2008) Source-level timing annotation and simulation for a heterogeneous multiprocessor. In: Proceedings of the conference on design, automation and test in Europe (DATE), Munich, Germany, pp 276–279. doi:10.1109/DATE.2008.4484897

    Chapter  Google Scholar 

  16. Oyamada M, Wagner F, Bonaciu M, Cesario W, Jerraya A (2007) Software performance estimation in MPSoC design. In: Design automation conference, pp 38–43. doi:10.1109/ASPDAC.2007.357789

    Google Scholar 

  17. Takashi N, Tomoaki T, Hiroshi N (2006) Design and implementation of a workload specific simulator. In: 39th annual symposium on simulation. doi:10.1109/ANSS.2006.19

    Google Scholar 

  18. Calder B, Austin T, Yang D, Sherwood T, Sair S, Newquist D, Cusac T (2004) BitRaker Anvil: binary instrumentation for rapid creation of simulation and workload analysis tools. In: Proceedings of the global signal processing (GSPx) Conference

    Google Scholar 

  19. Giusto P, Martin G, Harcourt E (2001) Reliable estimation of execution time of embedded software. In: Design, automation and test in Europe (DATE’2001). IEEE Press, Piscataway, pp 580–589. doi:10.1109/DATE.2001.915082

    Google Scholar 

  20. Bammi J, Harcourt E, Kruijtzer W, Lavagno L, Lazarescu M (2000) Software performance estimation strategies in a system-level design tool. In: Eighth international workshop on Hardware/Software codesign (CODES 2000), pp 82–86

    Google Scholar 

  21. Zivojnovic V, Meyr H (1996) Compiled HW/SW co-simulation. In: Proceedings of the design automation conference, DAC, pp 690–695. doi:10.1109/DAC.1996.545662

    Google Scholar 

  22. Suzuki K, Sangiovanni-Vincentelli A (1996) Efficient software performance estimation methods for hardware/software codesign. In: 33rd design automation conference (DAC), pp 605–610. doi:10.1109/DAC.1996.545647

    Google Scholar 

  23. Ball T, Larus J (1996) Efficient path profiling. In: MICRO-29, pp 46–57. doi:10.1109/MICRO.1996.566449

    Google Scholar 

  24. Mills C, Ahalt S, Fowler J (1991) Compiled instruction set simulation. Softw Pract Exp 21(8), 877–889. doi:10.1109/INTERA.2002.995841

    Article  Google Scholar 

  25. GNU Compiler Collection (GCC) documentation, http://gcc.gnu.org/

  26. ArchC Simulators. http://archc.org/

  27. LLVM Compiler Environment, http://llvm.org/

  28. TSIM Simulator for LEON processor, http://www.gaisler.com/

  29. RapidMiner Tool for Regression Analysis. http://rapid-i.com/

  30. PandA Framework for Hardware-Software Codesign, http://panda.dei.polimi.it/

  31. SimIt-ARM, Simulator for ARM, simit-arm.sourceforge.net/

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Correspondence to Rajendra Patel.

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Patel, R., Rajawat, A. Recent trends in embedded system software performance estimation. Des Autom Embed Syst 17, 193–213 (2013). https://doi.org/10.1007/s10617-013-9125-2

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