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Accurate age counter for wear leveling on non-volatile based main memory

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Abstract

Limited lifetime has been a key challenge in development of emerging non-volatile memories (NVM). Age counter based wear leveling is the most effective approach in the extension of their lifetime. The age counters in these approaches are determined by the number of writes to an NVM management unit, such as segment, page or block, to represent the wearing to the NVM unit. However, age counters in previous works have a key problem, which is not able to accurately represent the real wearing. In addition, traditional wear leveling approaches are also unaware of intra-unit non-uniform writes. For these reasons, the existing wear-leveling methods are limited for extending the lifetime of NVM. To address these problems, this paper proposes an accurate age counter increment mechanism, which is designed with the awareness of flags overlap between the write buffer and physical NVM unit. Flags overlap means that the dirty flags of the updated data are overlapping with the wearing flags of the physical page. In this case, the age counter is increased. For intra-unit non-uniform writes, it is released by the smartly designed write buffer. Cooperating with the proposed age counter, this paper further develops an accurate age counter-aware wear-leveling for non-volatile based main memory. Detailed simulations of 20 workloads show that the proposed mechanism is very encouraging. The accuracy of the proposed age counter is improved by 438.0 %, on average, compared to traditional age counters. In addition, we achieve 95.0 % of the lifetime to the theoretical maximum on average, while just incurring 8.1 % overhead compared to no wear leveling (baseline).

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References

  1. Apalkov D, Khvalkovskiy A, Watts S, Nikitin V, Tang X, Lottis D, Moon K, Luo X, Chen E, Ong A et al (2013) Spin-transfer torque magnetic random access memory (stt-mram). ACM J Emerg Technol Comput Syst (JETC) 9(2):13

    Google Scholar 

  2. Burger D, Austin TM (1997) The simplescalar tool set, version 2.0. ACM SIGARCH Comput Archit News 25(3):13–25

    Article  Google Scholar 

  3. Chang MF, Wu CW, Kuo CC, Shen SJ, Yang SM, Lin SF, Shen WC, King YC, Lin CJ, Chih YD (2013) A low-voltage bulk-drain-driven read scheme for sub-0.5 v 4 mb 65 nm logic-process compatible embedded resistive ram (reram) macro. Solid-State Circuits 4:597–599

    Google Scholar 

  4. Chang YH, Kuo TW (2009) A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems. In: DAC’09 46th ACM/IEEE design automation conference, pp. 858–863.

  5. Chen C.H., Hsiu P.C., Kuo T.W., Yang C.L., Wang C.Y.(2012) Age-based pcm wear leveling with nearly zero search cost. In: 49th ACM/EDAC/IEEE design automation conference (DAC), pp. 453–458.

  6. Choi Y, Song I, Park MH, Chung H, Chang S, Cho B, Kim J, Oh Y, Kwon D, Sunwoo J et al (2012) A 20nm 1.8 v 8gb pram with 40mb/s program bandwidth. In: 2012 IEEE international solid-state circuits conference digest of technical papers (ISSCC), pp. 46–48.

  7. Chua LO, Kang SM (1976) Memristive devices and systems. Proc IEEE 64(2):209–223

    Article  MathSciNet  Google Scholar 

  8. Ferreira AP, Zhou M, Bock S, Childers B, Melhem R, Mossé D (2010) Increasing pcm main memory lifetime. In: Proceedings of the conference on design, automation and test in Europe, pp. 914–919. European Design and Automation Association

  9. Hartmann M, Raghavan P, Perre LVD, Agrawal P, Dehaene W (2013) Memristor-based (reram) data memory architecture in asip design. In: 2013 Euromicro conference on digital system design (DSD), pp. 795–798. IEEE

  10. Hu J, Tseng WC, Xue CJ, Zhuge Q, Zhao Y, Sha EM (2011) Write activity minimization for nonvolatile main memory via scheduling and recomputation. IEEE Trans Comput-Aided Des Integr Circuits Syst 30(4):584–592

    Article  Google Scholar 

  11. Hu J, Zhuge Q, Xue CJ, Tseng WC, Sha EHM (2013) Software enabled wear-leveling for hybrid pcm main memory on embedded systems. In: IEEE design, automation and test in Europe conference and exhibition (DATE), pp. 599–602.

  12. Huang D, Tang YH (2013) Research on memristor oriented to resistive ram. Appl Mech Mater 427:974–977

    Article  Google Scholar 

  13. Ipek E, Condit J, Nightingale EB, Burger D, Moscibroda T (2010) Dynamically replicated memory: building reliable systems from nanoscale resistive memories. In: ACM SIGARCH computer architecture news, vol. 38, pp. 3–14. ACM

  14. Kryder MH, Kim CS (2009) After hard driveswhat comes next? IEEE Trans Magn 45(10):3406–3413

    Article  Google Scholar 

  15. Kultursay E, Kandemir M, Sivasubramaniam A, Mutlu O (2013) Evaluating stt-ram as an energy-efficient main memory alternative. In: Proceedings of the IEEE international symposium on performance analysis of systems and software (ISPASS)

  16. Lee BC, Ipek E, Mutlu O, Burger D (2009) Architecting phase change memory as a scalable dram alternative. ACM SIGARCH Comput Archit News 37(3):2–13

    Article  Google Scholar 

  17. Li J, Ndai P, Goel A, Liu H, Roy K (2009) An alternate design paradigm for robust spin-torque transfer magnetic ram (stt mram) from circuit/architecture perspective. In: Proceedings of the 2009 Asia and South Pacific design automation conference. IEEE Press, pp. 841–846

  18. Long L, Liu D, Hu J, Gu S, Zhuge Q, Sha EM (2013) A space-based wear leveling for pcm-based embedded systems. In: 2013 IEEE 19th international conference on embedded and real-time computing systems and applications (RTCSA), pp. 145–148

  19. Micron: Nand flash. http://www.micron.com/products/nand-flash (2013)

  20. Mogul JC, Argollo E, Shah MA, Faraboschi P (2009) Operating system support for nvm+ dram hybrid main memory. In: HotOS

  21. Nishi Y (2011) Challenges and opportunities for future non-volatile memory technology. Curr Appl Phys 11(2):e101–e103

    Article  MathSciNet  Google Scholar 

  22. Qureshi MK, Karidis J, Franceschini M, Srinivasan V, Lastras L, Abali B(2009) Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling. In: Proceedings of the 42nd annual IEEE/ACM international symposium on microarchitecture. ACM, pp. 14–23.

  23. Qureshi MK, Srinivasan V, Rivers JA (2009) Scalable high performance main memory system using phase-change memory technology. ACM SIGARCH Comput Archit News 37(3):24–33

    Article  Google Scholar 

  24. Roberts D, Kgil T, Mudge T (2009) Using non-volatile memory to save energy in servers. In: Proceedings of the conference on design, automation and test in Europe. European Design and Automation Association, pp. 743–748.

  25. Russo U, Redaelli A, Bez R et al (2010) Non-volatile memory technology overview. In: Workshop on technology architecture interaction (WTAI)

  26. Seong NH, Woo DH, Lee HHS (2010) Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. In: ACM SIGARCH computer architecture news, vol. 38, pp. 383–394. ACM

  27. Shi L, Xue CJ, Hu J, Tseng WC, Zhou X, Sha EHM (2010) Write activity reduction on flash main memory via smart victim cache. In: Proceedings of the 20th symposium on great lakes symposium on VLSI. ACM, pp. 91–94.

  28. Simpson R, Fons P, Kolobov A, Fukaya T, Krbal M, Yagi T, Tominaga J (2011) Interfacial phase-change memory. Nat Nanotechnol 6(8):501–505

    Article  Google Scholar 

  29. Tian W, Li J, Zhao Y, Xue CJ, Li M, Chen E (2011) Optimal task allocation on non-volatile memory based hybrid main memory. In: Proceedings of the 2011 ACM symposium on research in applied computation. ACM, pp. 1–6.

  30. Wu X, Li J, Zhang L, Speight E, Rajamony R, Xie Y (2009) Hybrid cache architecture with disparate memory technologies. In: ACM SIGARCH computer architecture news, vol. 37, pp. 34–45.

  31. Wu X, Li J, Zhang L, Speight E, Xie Y (2009) Power and performance of read-write aware hybrid caches with non-volatile memories. In: DATE’09 IEEE design, automation and test in Europe conference and exhibition, pp. 737–742.

  32. Xue CJ, Zhang Y, Chen Y, Sun G, Yang JJ, Li H (2011) Emerging non-volatile memories: opportunities and challenges. In: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis. ACM, pp. 325–334. ACM

  33. Yang JJ, Pickett MD, Li X, Ohlberg DA, Stewart DR, Williams RS (2008) Memristive switching mechanism for metal/oxide/metal nanodevices. Nat Nanotechnol 3(7):429–433

    Article  Google Scholar 

  34. Zhou P, Zhao B, Yang J, Zhang Y (2009) A durable and energy efficient main memory using phase change memory technology. In: ACM SIGARCH computer architecture news, vol. 37, pp. 14–23. ACM

  35. Zhou X, Wu L, Song Z, Rao F, Ren K, Peng C, Song S, Liu B, Xu L, Feng S (2013) Phase transition characteristics of al-sb phase change materials for phase change memory application. Appl Phys Lett 103(7):072,114-1–072,114

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Acknowledgments

This work is partially supported by National 863 Program 2013AA013202, Chongqing cstc2012ggC40005, NSFC 61173014, NSF CNS-1015802.

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Correspondence to Liang Shi.

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Luo, H., Zhuge, Q., Shi, L. et al. Accurate age counter for wear leveling on non-volatile based main memory. Des Autom Embed Syst 17, 543–564 (2013). https://doi.org/10.1007/s10617-014-9141-x

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  • DOI: https://doi.org/10.1007/s10617-014-9141-x

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