Abstract
The demands of system complexity and design productivity for embedded systems can be managed by simplifying and reusing the design. Furthermore, these systems should be verified as early as possible in the development process to reduce the cost and effort. The rationale of the proposed framework in this article is to simplify the design and verification process of embedded systems in the context of Model Based System Engineering (MBSE). To achieve this, UML profile for SystemVerilog (UMLSV) is proposed to model the design and verification requirements. Particularly, we introduce various UMLSV stereotypes to model the system design (structure and behavior). Furthermore, a temporal extension of Object Constraint Language is used to capture the verification requirements (properties/constraints) in UMLSV. Consequently, the proposed framework allows the modeling of system design (structure and behavior) along with the verification aspects at higher abstraction level. Following the MBSE process, the high-level models and the verification constraints are transformed into synthesizable SystemVerilog Register Transfer Level and SystemVerilog Assertions code. This leads to perform the Assertions Based Verification of system design in the early development phases by using state-of-the-art simulators. The effectiveness of the proposed framework is demonstrated with the help of multiple case studies including Traffic Lights Controller, Unmanned Aerial Vehicle, Elevator and Car Collision Avoidance System.
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References
Driver C, Reilly S, Linehan E, Cahill V, Clarke S (2010) Managing embedded systems complexity with aspect-oriented model-driven engineering. ACM Trans Embed Comput Syst (TECS) 10(2):21. https://doi.org/10.1145/1880050.1880057
Guillet S, De Lamotte F, Le Griguer N, Rutten E, Gogniat G, Diguet J-P (2014) Extending UML/MARTE to support discrete controller synthesis, application to reconfigurable systems-on-chip modeling. ACM Trans Reconfigurable Technol Syst 7(3):27. https://doi.org/10.1145/2629628
Lecomte S, Guillouard S, Moy C, Leray P, Soulard P (2011) A co-design methodology based on model driven architecture for real time embedded systems. Math Comput Model 53(3–4):471–484. https://doi.org/10.1016/j.mcm.2010.03.035
Object Management Group (2018) Unified modeling language standard. https://www.omg.org/spec/UML/2.5/About-UML/. Accesses Feb 2018
Rashid M, Anwar MW, Khan AM (2015) Towards the tools selection in model based system engineering for embedded systems—a systematic literature review. J Syst Softw (JSS) 106:150–163
Luciano L, Grant M, Bran S (2003) UML for real: design of embedded real-time systems. Springer, Berlin
Rashid M, Anwar MW, Azam F, Kashif M (2016) Model-based requirements and properties specifications trends for early design verification of embedded systems. In: IEEE 11th system of systems engineering conference (SoSE) 2016
Bengtsson JE, Yi W (2004) Timed automata: semantics, algorithms and tools. In: Desel J, Reisig W, Rozenberg G (eds) ACPN 2003, vol 3098. LNCS. Springer, Heidelberg, pp 87–124
Spivey JM (1992) The Z notation: a reference manual. Prentice-Hall, Englewood Cliffs
IEEE SystemVerilog Standard 1800–2009. http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5354133. Accessed Oct 2018
Fitzpatrick T (2004) SystemVerilog for VHDL users. In: Proceedings of the design, automation and test in Europe conference and exhibition (DATE)
Sohofi H, Navabi Z (2015) System-level assertions: approach for electronic system-level verification. IET Comput Digit Tech 9(3):142–152
Accellera Universal Verification Methodology Standard. http://www.accellera.org/downloads/standards/uvm. Accessed Nov 2018
Mentor Graphics Questa SIM. http://www.mentor.com/products/fv/questa/. Accessed Mar 2018
Kim K (2014) Functional verification of a safety class controller For NPPs using a UVM register model. J Nucl Eng Technol 46(3):381–386
Schamai W (2009) Modelica modeling language (ModelicaML) a UML profile for Modelica. Technical report 2009:5, EADS IW, Germany, Linkoping University, Sweden
Ni S, Zhuang Y, Cao Z, Kong X (2015) Modeling dependability features for real-time embedded systems. IEEE Trans Dependable Secur Comput 12(2):190–203
Grant M, Wolfgang M (2005) UML for SOC design. Springer, Berlin
Grotker T, Liao S, Martin G, Swan S (2002) System design with SystemC. Springer, Berlin
Anwar MW, Rashid M, Azam F, Kashif M (2017) Model-based design verification for embedded systems through SVOCL: an OCL extension for SystemVerilog. Int J Des Autom Embed Syst 21(1):1–36
Object Management Group (2012) OMG system modeling language specification. http://www.omg.org/spec/SysML/1.3/. Accessed 6 Mar 2012
Papyrus Modeling Editor. http://www.eclipse.org/modeling/mdt/papyrus/. Accessed Dec 2018
UMLSV Guidelines. http://modeves.com/umlsvman.html. Accessed Dec 2018
Magic Draw. http://www.nomagic.com/products/magicdraw.html. Accessed Aug 2018
Eclipse Acceleo (M2T). https://eclipse.org/acceleo/. Accessed Dec 2018
Quadri IR, Brosse E, Gray I, Matragkas N, Indrusiak LS, Rossi M, Bagnato A, Sadovykh A (2012) MADES FP7 EU project: effective high level SysML/MARTE methodology for real-time and embedded avionics systems. In: 7th international workshop reconfigurable communication-centric systems-on-chip (ReCoSoC) 2012, pp 1–8. https://doi.org/10.1109/recosoc.2012.6322882
Gamatié A, Le Beux S, Piel É, Ben Atitallah R, Etien A, Marquet P, Dekeyser JL (2011) A model-driven design framework for massively parallel embedded systems. ACM Trans Embed Comput Syst (TECS) 10(4):39. https://doi.org/10.1145/2043662.2043663
Eclipse Model-to-Text Project—JET. https://www.eclipse.org/modeling/m2t/. Accessed Apr 2018
UMLSV Transformation Engine with sample case studies. http://modeves.com/umlsvte.html. Accessed Nov 2017
UMLSV Profile (2018) Design verification details. http://www.modeves.com/dvquesta.html. Accessed Oct 2018
Xilinx Vivado Design Suite. http://www.xilinx.com/products/design-tools/vivado.html. Accessed Feb 2017
Baresi L, Morzenti A, Motta A, Rossi M (2017) A logic-based approach for the verification of UML timed models. ACM Trans Softw Eng Methodol (TOSEM) 26(2):7
Linehan E, Clarke S (2012) An aspect-oriented, model-driven approach to functional hardware verification. J Syst Archit 58(5):195–208. https://doi.org/10.1016/j.sysarc.2011.02.001
IEEE computer society, IEEE std 1647-2008, IEEE standard for the functional verification language e., Standard IEEE Std 1647-2008, IEEE, NY, USA, August 2008
Formal Dynamic Semantics of the Modelling Notation (2010) Technical Report. http://www.mades-project.org/
Di Guglielmo G, Di Guglielmo L, Foltinek A, Fujita M, Fummi F, Marconcini C, Pravadelli G (2013) On the integration of model-driven design and dynamic assertion-based verification for embedded software. J Syst Softw 86(8):2013–2033. https://doi.org/10.1016/j.jss.2012.08.061
Besnard L, Gautier T, Le Guernic P, Talpin JP (2010) Compilation of polychronous data flow equations. In: Shukla S, Talpin JP (eds) Correct-by-construction embedded software synthesis: formal frameworks, methodologies, and tools. Springer, Berlin
Bernardi S, Flammini F, Marrone S, Mazzocca N, Merseguer J, Nardone R, Vittorini V (2013) Enabling the usage of UML in the verification of railway systems: the DAM-rail approach. Reliab Eng Syst Saf 120:112–126. https://doi.org/10.1016/j.ress.2013.06.032
Raiteri DC, Iacono M, Franceschinis G, Vittorini V (2004) Repairable fault tree for the automatic evaluation of repair policies. In: Proceedings of the 2004 international conference on dependable systems and networks, pp 659–68
Charniak E (1991) Bayesian networks without tears: making Bayesian networks more accessible to the probabilistically unsophisticated. AIMagazine 12(4):50–63
Marsan MA, Balbo G, Conte G, Donatelli S, Franceschinis G (1995) Modelling with generalized stochastic petri nets. Wiley series in parallel computing. Wiley, Hoboken
Guillet S, De Lamotte F, Le Griguer N, Rutten E, Gogniat G, Diguet JP (2014) Extending UML/MARTE to support discrete controller synthesis, application to reconfigurable systems-on-chip modeling. ACM Trans Reconfigurable Technol Syst 7(3):27. https://doi.org/10.1145/2629628
Delaval G, Marchand H, Rutten E (2010) Contracts for modular discrete controller synthesis. In: Proceedings of the ACM SIGPLAN/SIGBED conference on languages, compilers, and tools for embedded systems (LCTES’10). ACM Press, New York, pp 57–66
Zhang H, Jiang Y, Liu H, Zhang H, Gu M, Sun J (2016) Model driven design of heterogeneous synchronous embedded systems. In: 31st IEEE/ACM international conference on automated software engineering (ASE)
Zhang H, Li G, Sun D, Lu Y, Hsu CH (2017) Verifying cooperative software: a SMT-based bounded model checking approach for deterministic scheduler. J Syst Archit 81:7–16
Marcello MM, García-Valls M (2018) Online verification in cyber-physical systems: practical bounds for meaningful temporal costs. J Softw Evol Process 30(3):1–25
Fathabadi AS, Butler MJ, Yang S, Maeda-Nunez LA, Bantock J, Al-Hashimi BM, Merrett GV (2018) A model-based framework for software portability and verification in embedded power management systems. J Syst Archit 82:12–23
Selic B (1998) Using UML for modeling complex real-time systems. In: Languages, compliers and tools for embedded systems (LCTES) 1998, pp 250–260
OMG fUML—Foundational UML standard. https://www.omg.org/spec/FUML/. Accessed Oct 2018
Ciccozzi F, Malavolta I, Selic B (2018) Execution of UML models: a systematic review of research and practice. J Softw Syst Model 18:2313–2360
Ebeid E, Quaglia D, Fummi F (2012) Generation of SystemC/TLM code from UML/MARTE sequence diagrams for verification. In: IEEE 15th international symposium on design and diagnostics of electronic circuits and systems (DDECS) 2012, pp 187–190. https://doi.org/10.1109/ddecs.2012.6219051
Banerjeey A, Ray S, Dasgupta P, Chakrabarti PP (2012) A dynamic assertion-based verification platform for validation of UML designs. ACM SIGSOFT Softw Eng Notes 37(1):1–14. https://doi.org/10.1145/2088883.2088891
Drusinsky D, Michael JB, Otani TW, Shing MT (2008) Validating UML statechart-based assertions libraries for improved reliability and assurance. In: Second international conference on secure system integration and reliability improvement 2008, pp 47–51. https://doi.org/10.1109/ssiri.2008.54
Accellera Portable Test and Stimulus Standard (PSS). https://www.accellera.org/downloads/standards/portable-stimulus. Accessed Sept 2019
Cadence Perspec System Verifier. https://www.cadence.com/content/cadence-www/global/en_US/home/tools/system-design-and-verification/software-driven-verification/perspec-system-verifier.html. Accessed Sept 2019
Mentor Graphics Questa inFact Tool. https://www.mentor.com/products/fv/infact/. Accessed Sept 2019
Acknowledgements
This project is funded by NSTIP (National Science Technology, Innovative Plan), Saudi Arabia under the Technology Area “Information Technology Strategic Priorities” and Track “Software Engineering and Innovated Systems”. We acknowledge the support of KACST (King Abdul-Aziz City for Science and Technology) and STU (Science and Technology Unit) Makkah.
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Anwar, M.W., Rashid, M., Azam, F. et al. A model-driven framework for design and verification of embedded systems through SystemVerilog. Des Autom Embed Syst 23, 179–223 (2019). https://doi.org/10.1007/s10617-019-09229-y
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DOI: https://doi.org/10.1007/s10617-019-09229-y