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CAD synthesis tools for floating-gate SoC FPAAs

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Abstract

We present a tool framework to compile and program mixed-signal circuits and systems on Floating-Gate (FG) based mixed-signal System-on-Chips (SoC) consisting of a digital processor and Field Programmable Analog Array (FPAA) fabric. We have modified the configuration of Verilog-to-Routing (VTR) to cover analog circuits and developed a tool called vpr2swcs to create the list of FG switches, that is going from a high level block description of the system to the addresses and bias values on the SoC. This tool enables users to generate macro blocks and customize block location while designing mixed-signal systems on the FPAA and also enables using routing fabric, composed of FGs, for Vector Matrix Multiplication (VMM), a computing element for an analog neural network. The paper demonstrates system level examples using this tool flow, where the experimental results have been proved in other publications.

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Notes

  1. http://users.ece.gatech.edu/phasler/FPAAtool/index.html.

References

  1. Betz V, Rose J, Marquardt A (2012) Architecture and CAD for deep-submicron FPGAs, vol 497. Springer, Berlin

    Google Scholar 

  2. Rose J, Luu J, Yu CW, Densmore O, Goeders J, Somerville A, Kent KB, Jamieson P, Anderson J (2012) “The VTR project: Architecture and CAD for FPGAs from verilog to routing,” In: Proceedings of the ACM/SIGDA international symposium on field programmable gate arrays, ser. FPGA ’12. New York, NY, USA: ACM, 2012, pp 77–86

  3. Kim J, Kim KT, Chung E-Y (2018) “Cad tool flow for variation-tolerant non-volatile stt-mram lut based fpga,” In: Proceedings of the 2018 7th international conference on software and computer applications, 2018, pp 312–316

  4. Saegusa T, Maruyama T, Yamaguchi Y (2008) “How fast is an fpga in image processing?” In: 2008 international conference on field programmable logic and applications. IEEE, 2008, pp 77–82

  5. Nurvitadhi E, Venkatesh G, Sim J, Marr D, Huang R, Ong Gee Hock J, Liew YT, Srivatsan K, Moss D, Subhaschandra S et al. (2017) “Can fpgas beat gpus in accelerating next-generation deep neural networks?” In: Proceedings of the 2017 ACM/SIGDA international symposium on field-programmable gate arrays, pp 5–14

  6. Ma Y, Cao Y, Vrudhula S, Seo J-s (2018) Optimizing the convolution operation to accelerate deep neural networks on fpga. IEEE Trans Very Large Scale Integr (VLSI) Syst 26(7):1354–1367

    Article  Google Scholar 

  7. Kutz HM, Williams TJ, Sullam BS, Snyder WS, Shutt JH, Byrkett BE, Mar M, Thiagarajan E, Kohagen NW, Wright DG et al. (2019) “Combined analog architecture and functionality in a mixed-signal array,” Jul. 2019, uS Patent 10,345,377

  8. George S, Kim S, Shah S, Hasler J, Collins M, Adil F, Wunderlich R, Nease S, Ramakrishnan S (2016) A programmable and configurable mixed-mode FPAA SoC. IEEE Trans Very Large Scale Integr (VLSI) Syst 24(6):2253–2261

    Google Scholar 

  9. Collins M, Hasler J, George S (2016) An open-source tool set enabling analog-digital-software co-design. J Low Power Electron Appl 6(1):3

    Article  Google Scholar 

  10. Kim S, Hasler J, George S (2016) Integrated floating-gate programming environment for system-level ICs. IEEE Trans Very Large Scale Integr (VLSI) Syst 24(6):2244–2252

    Google Scholar 

  11. Kim S, Shah S, Hasler J (2017) Calibration of floating-gate soc fpaa system. IEEE Trans Very Large Scale Integration (VLSI) Syst 25(9):2649–2657

    Article  Google Scholar 

  12. Hasler J, Natarajan A, Shah S, Kim S (2017) “Soc fpaa immersed junior level circuits course,” In: 2017 IEEE international conference on microelectronic systems education (MSE), May 2017, pp 7–10

  13. Hasler J, Shah S, Kim S, Lal IK, Collins M (2016) Remote system setup using large-scale field programmable analog arrays (fpaa) to enabling wide accessibility of configurable devices. J Low Power Electron Appl 6(3):14

    Article  Google Scholar 

  14. Mead C (1990) Neuromorphic electronic systems. Proc IEEE 78(10):1629–1636

    Article  Google Scholar 

  15. Hasler J, Marr H (2013) Finding a roadmap to achieve large neuromorphic hardware systems. Front Neurosci 7:118

    Article  Google Scholar 

  16. Shah S, Teague CN, Inan OT, Hasler J (2016) “A proof-of-concept classifier for acoustic signals from the knee joint on a fpaa,” In: 2016 IEEE SENSORS, Oct 2016, pp 1–3

  17. Koziol S, Hasler P, Stilman M (2012) “Robot path planning using field programmable analog arrays,” In: 2012 IEEE international conference on robotics and automation, May 2012, pp 1747–1752

  18. Enterprises S et al (2012) Scilab: Free and open source software for numerical computation. Scilab Enterprises, Orsay, France, p 3

    Google Scholar 

  19. Luu J, Goeders J, Wainberg M, Somerville A, Yu T, Nasartschuk K, Nasr M, Wang S, Liu T, Ahmed N, Kent KB, Anderson J, Rose J, Betz V (2014) VTR 7.0: Next generation architecture and CAD system for FPGAs. ACM Trans Reconfigurable Technol Syst 7(2):6:1-6:30

    Article  Google Scholar 

  20. Berkeley U (1992) Berkeley logic interchange format (blif). Oct Tools Distrib 2:197–247

    Google Scholar 

  21. Doboli A, Vemuri R (2003) Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies. IEEE Trans Comput-Aided Des Integr Circuits Syst 22(11):1556–1568

    Article  Google Scholar 

  22. Baskaya F, Anderson DV, Hasler P, Lim SK (2009) “A generic reconfigurable array specification and programming environment (grasper),” In: 2009 European conference on circuit theory and design, Aug 2009, pp 619–622

  23. Baskaya F, Reddy S, Lim SK, Anderson DV (2006) Placement for large-scale floating-gate field-programable analog arrays. IEEE Trans Very Large Scale Integr (VLSI) Syst 14(8):906–910

    Article  Google Scholar 

  24. Hasler J, Kim S, Adil F (2016) Scaling floating-gate devices predicting behavior for programmable and configurable circuits and systems. J Low Power Electron Appl 6(3):13

    Article  Google Scholar 

  25. Ramakrishnan S, Hasler J (2014) Vector-matrix multiply and winner-take-all as an analog classifier. IEEE Trans Very Large Scale Integr (VLSI) Syst 22(2):353–361

    Article  Google Scholar 

  26. Schlottmann CR, Shapero S, Nease S, Hasler P (2012) A digitally enhanced dynamically reconfigurable analog platform for low-power signal processing. IEEE J Solid-State Circuits 47(9):2174–2184

    Article  Google Scholar 

  27. Natarajan A, Hasler J (2017) Modeling, simulation and implementation of circuit elements in an open-source tool set on the fpaa. Analog Integr Circuits Signal Process 91(1):119–130

    Article  Google Scholar 

  28. Dongarra JJ, Luszczek P, Petitet A (2003) The linpack benchmark: past, present and future. Concurr Comput: Practice Exp 15(9):803–820

    Article  Google Scholar 

  29. Hasler J (2016) “Opportunities in physical computing driven by analog realization,” In: 2016 IEEE international conference on rebooting computing (ICRC), Oct 2016, pp 1–8

  30. Ovtcharov K, Ruwase O, Kim J-Y, Fowers J, Strauss K, Chung ES (2015) Accelerating deep convolutional neural networks using specialized hardware. Microsoft Res Whitepaper 2(11):1–4

    Google Scholar 

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Acknowledgements

The authors would like to thank Suma George for her help while debugging the tools at the early stage of development and Sung Kyu Lim for valuable comments and advice on the tools.

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Authors and Affiliations

  1. School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA

    Sihwan Kim, Sahil Shah, Richard Wunderlich & Jennifer Hasler

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  1. Sihwan Kim
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  2. Sahil Shah
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  3. Richard Wunderlich
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  4. Jennifer Hasler
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Correspondence to Jennifer Hasler.

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Kim, S., Shah, S., Wunderlich, R. et al. CAD synthesis tools for floating-gate SoC FPAAs. Des Autom Embed Syst 25, 161–176 (2021). https://doi.org/10.1007/s10617-021-09247-9

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