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Optimal low-power coding for error correction and crosstalk avoidance in on-chip data buses

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Abstract

Coupled switched capacitance causes crosstalk in ultra deep submicron/nanometer VLSI fabrication, which leads to power dissipation, delay faults, and logical malfunctions. We present the first memoryless transition bus-encoding technique for power minimization, error-correction, and elimination of crosstalk simultaneously. To accomplish this, we generalize balanced sampling plans avoiding adjacent units, which are widely used in the statistical design of experiments. Optimal or asymptotically optimal constant weight codes eliminating each kind of crosstalk are constructed.

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Authors and Affiliations

  1. Division of Mathematical Sciences, School of Physical and Mathematical Sciences, Nanyang Technological University, Singapore, 637371, Singapore

    Yeow Meng Chee, Hui Zhang & Xiande Zhang

  2. School of Computing, Informatics, and Decision Systems Engineering, Arizona State University, Tempe, AZ, 85287, USA

    Charles J. Colbourn

  3. Department of Computer Science, University of Vermont, Burlington, VT, 05405, USA

    Alan Chi Hung Ling

Authors
  1. Yeow Meng Chee
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  2. Charles J. Colbourn
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  3. Alan Chi Hung Ling
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  4. Hui Zhang
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  5. Xiande Zhang
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Correspondence to Charles J. Colbourn.

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This is one of several papers published in Designs, Codes and Cryptography comprising the “Special Issue on Cryptography, Codes, Designs and Finite Fields: In Memory of Scott A. Vanstone”.

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Chee, Y.M., Colbourn, C.J., Ling, A.C.H. et al. Optimal low-power coding for error correction and crosstalk avoidance in on-chip data buses. Des. Codes Cryptogr. 77, 479–491 (2015). https://doi.org/10.1007/s10623-015-0084-4

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