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Controller synthesis for dynamic hierarchical real-time plants using timed automata

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Abstract

We use timed I/O automata based timed games to synthesize task-level reconfiguration services for cost-effective fault tolerance in a case study. The case study shows that state-space explosion is a severe problem for timed games. By applying suitable abstractions, we dramatically improve the scalability. However, timed I/O automata do not facilitate algorithmic abstraction generation techniques. The case study motivates the development of timed process automata to improve modeling and analysis for controller synthesis of time-critical plants which can be hierarchical and dynamic. The model offers two essential features for industrial systems: (i) compositional modeling with reusable designs for different contexts, and (ii) state-space reduction technique. Timed process automata model dynamic networks of continuous-time communicating plant processes which can activate other plant processes. We show how to establish safety and reachability properties of timed process automata by reduction to solving timed games. To mitigate the state-space explosion problem, an algorithmic state-space reduction technique using compositional reasoning and aggressive abstractions is also proposed. In this article, we demonstrate the theoretical framework of timed process automata and the effectiveness of the proposed state-space reduction technique by extending the case study.

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Notes

  1. More generally, the communication can be abstracted by suitable understanding of worst and best case execution times, and terminations are independent of communication.

  2. To show clearer impacts of different modeling aspects on the analysis, we picked some imaginary system configurations instead of some actual system configurations.

  3. To avoid clutter, we abuse notation by writing P instead of id(P).

  4. A P is the set of actions where action names are constructed using regular expression (P “.” C∣channel(P)) “.” A.

  5. The use of non-negative finitely bounded integer variables can be avoided if a more cumbersome encoding is used.

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Authors and Affiliations

  1. Research & Advanced Engineering, Ford Motor Company, Dearborn, MI, USA

    Md Tawhid Bin Waez

  2. Computer Science Department, IT University of Copenhagen, København, Denmark

    Andrzej Wąsowski

  3. School of Computing, Queen’s University, Kingston, ON, Canada

    Juergen Dingel

  4. Department of Electrical and Computer Engineering, Queen’s University, Kingston, ON, Canada

    Karen Rudie

Authors
  1. Md Tawhid Bin Waez
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  2. Andrzej Wąsowski
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  3. Juergen Dingel
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  4. Karen Rudie
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Correspondence to Md Tawhid Bin Waez.

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Waez, M.T.B., Wąsowski, A., Dingel, J. et al. Controller synthesis for dynamic hierarchical real-time plants using timed automata. Discrete Event Dyn Syst 27, 407–441 (2017). https://doi.org/10.1007/s10626-017-0240-2

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