Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation

Abstract

This paper presents a novel fault simulation environment in VHDL. By writing a library of special fault simulation models, a traditional model is transformed into a new model that performs fault simulation using a VHDL simulation engine. Pre- and post-synthesis VHDL models are used for an effective implementation, better performance and to minimize the overhead associated with VHDL simulation. Models are written such that an automatic switching mechanism selects gate level descriptions for originating faults and behavioral descriptions for propagating them.