Abstract
This paper describes a new Built-In-Self-Test(BIST) scheme for estimation of static non-linearity errors in segmented and binary weighted digital to analog converters (DACs). The BIST scheme comprises of a hierarchy of tests including tests for non-monotonicity, checks to detect if the DNL/INL errors exceed ±0.5 LSB and actual estimation of the DNL/INL. The BIST scheme has been experimentally verified on 10-bit segmented current steering DAC. The DAC, along with the additional circuits required for testing, was designed and fabricated using a 0.35 μm process. Both simulation and experimental results are included in this paper. Errors estimated using the BIST scheme match well with measurements done on the fabricated device.
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Rafeeque K.P., S., Vasudevan, V. A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs. J Electron Test 20, 623–638 (2004). https://doi.org/10.1007/s10677-004-4250-4
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DOI: https://doi.org/10.1007/s10677-004-4250-4