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A three-step decomposition method for the evolutionary design of sequential logic circuits

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Abstract

Evolvable hardware (EHW) refers to an automatic circuit design approach, which employs evolutionary algorithms (EAs) to generate the configurations of the programmable devices. The scalability is one of the main obstacles preventing EHW from being applied to real-world applications. Several techniques have been proposed to overcome the scalability problem. One of them is to decompose the whole circuit into several small evolvable sub-circuits. However, current techniques for scalability are mainly used to evolve combinational logic circuits. In this paper, in order to decompose a sequential logic circuit, the state decomposition, output decomposition and input decomposition are united as a three-step decomposition method (3SD). A novel extrinsic EHW system, namely 3SD–ES, which combines the 3SD method with the (μ, λ) ES (evolution strategy), is proposed, and is used for the evolutionary designing of larger sequential logic circuits. The proposed extrinsic EHW system is tested extensively on sequential logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library. The results demonstrate that 3SD–ES has much better performance in terms of scalability. It enables the evolutionary designing of larger sequential circuits than have ever been evolved before.

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Acknowledgments

This work is partly supported by the National Natural Science Foundation of China (No.60404004), and the 2006-2007 Excellent Young and Middle-aged Academic Leader Development Program of Anhui Province Research Experiment Bases. We are thankful to the anonymous reviewers for their valuable comments that help us to improve the quality of this paper.

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Correspondence to Wenjian Luo.

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Liang, H., Luo, W. & Wang, X. A three-step decomposition method for the evolutionary design of sequential logic circuits. Genet Program Evolvable Mach 10, 231–262 (2009). https://doi.org/10.1007/s10710-009-9083-4

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