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Learning heuristics for basic block instruction scheduling

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Abstract

Instruction scheduling is an important step for improving the performance of object code produced by a compiler. A fundamental problem that arises in instruction scheduling is to find a minimum length schedule for a basic block—a straight-line sequence of code with a single entry point and a single exit point—subject to precedence, latency, and resource constraints. Solving the problem exactly is known to be difficult, and most compilers use a greedy list scheduling algorithm coupled with a heuristic. The heuristic is usually hand-crafted, a potentially time-consuming process. In contrast, we present a study on automatically learning good heuristics using techniques from machine learning. In our study, a recently proposed optimal basic block scheduler was used to generate the machine learning training data. A decision tree learning algorithm was then used to induce a simple heuristic from the training data. The automatically constructed decision tree heuristic was compared against a popular critical-path heuristic on the SPEC 2000 benchmarks. On this benchmark suite, the decision tree heuristic reduced the number of basic blocks that were not optimally scheduled by up to 55% compared to the critical-path heuristic, and gave improved performance guarantees in terms of the worst-case factor from optimality.

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References

  • Blainey, R.J.: Instruction scheduling in the TOBEY compiler. IBM J. Res. Dev. 38(5), 577–593 (1994)

    Google Scholar 

  • Cooper, K.D., Torczon, L.: Engineering a Compiler. Morgan Kaufmann, San Mateo (2004)

    Google Scholar 

  • Dorndorf, U.: Project Scheduling with Time Windows. Physica-Verlag, Heidelberg (2002)

    MATH  Google Scholar 

  • Govindarajan, R.: Instruction scheduling. In: Srikant, Y.N., Shankar, P. (eds.) The Compiler Design Handbook, pp. 631–687. CRC Press, Boca Raton (2003)

    Google Scholar 

  • Guyon, I., Elisseeff, A.: An introduction to variable and feature selection. J. Mach. Learn. Res. 3, 1157–1182 (2003)

    Article  MATH  Google Scholar 

  • Hennessy, J., Patterson, D.: Computer Architecture: A Quantitative Approach, 3rd edn. Morgan Kaufmann, San Mateo (2003)

    Google Scholar 

  • Hoxey, S., Karim, F., Hay, B., Warren, H.: The PowerPC Compiler Writer’s Guide. Warthman Associates (1996)

  • Lee, C., Potkonjak, M., Manginoe-Smith, W.: MediaBench: A tool for evaluating and synthesizing multimedia and communications. In: Proceedings of the 30th Annual IEEE/ACM International Symposium on Microarchitecture (Micro-30), pp. 330–335. Research Triangle Park, North Carolina (1997)

  • Li, X., Olafsson, S.: Discovering dispatching rules using data mining. J. Sched. 8, 515–527 (2005)

    Article  MATH  MathSciNet  Google Scholar 

  • Malik, A.M., McInnes, J., van Beek, P.: Optimal basic block instruction scheduling for multiple-issue processors using constraint programming. Technical Report CS-2005-19, School of Computer Science, University of Waterloo (2005)

  • McGovern, A., Moss, J.E.B., Barto, A.G.: Building a basic block instruction scheduler using reinforcement learning and rollouts. Mach. Learn. 49(2/3), 141–160 (2002)

    Article  MATH  Google Scholar 

  • Moss, J.E.B., Utgoff, P.E., Cavazos, J., Precup, D., Stefanovic, D., Brodley, C., Scheef, D.: Learning to schedule straight-line code. In: Proceedings of the 10th Conference on Advances in Neural Information Processing Systems (NIPS), pp. 929–935. Denver, Colorado (1997)

  • Muchnick, S.: Advanced Compiler Design and Implementation. Morgan Kaufmann, San Mateo (1997)

    Google Scholar 

  • Neumann, K., Schwindt, C., Zimmermann, J.: Project Scheduling with Time Windows and Scarce Resources, 2nd edn. Springer, Berlin (2003)

    MATH  Google Scholar 

  • Pinedo, M.: Scheduling: Theory, Algorithms, and Systems. Prentice Hall, New York (1995)

    MATH  Google Scholar 

  • Quinlan, J.R.: C4.5: Programs for Machine Learning. Morgan Kaufmann, San Mateo (1993). The C4.5 software is available at: http://www.cse.unsw.edu.au/ quinlan/

    Google Scholar 

  • Shieh, J.-J., Papachristou, C.: On reordering instruction streams for pipelined computers. SIGMICRO Newsl. 20(3), 199–206 (1989)

    Article  Google Scholar 

  • Shobaki, G., Wilken, K.: Optimal superblock scheduling using enumeration. In: Proceedings of the 37th Annual IEEE/ACM International Symposium on Microarchitecture (Micro-37), pp. 283–293. Portland, Oregon (2004)

  • Smotherman, M., Krishnamurthy, S., Aravind, P.S., Hunnicutt, D.: Efficient DAG construction and heuristic calculation for instruction scheduling. In: Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture (Micro-24), pp. 93–102. Albuquerque, New Mexico (1991)

  • Tiemann, M.D.: The GNU instruction scheduler (1989)

  • van Beek, P., Wilken, K.: Fast optimal instruction scheduling for single-issue processors with arbitrary latencies. In: Proceedings of the Seventh International Conference on Principles and Practice of Constraint Programming, pp. 625–639. Paphos, Cyprus (2001)

  • Warren, H.S. Jr.: Instruction scheduling for the IBM RISC System/6000 processor. IBM J. Res. Dev. 34(1), 85–92 (1990)

    Article  MathSciNet  Google Scholar 

  • Witten, I.H., Frank, E.: Data Mining. Morgan Kaufmann, San Mateo (2000)

    Google Scholar 

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Correspondence to Peter van Beek.

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Malik, A.M., Russell, T., Chase, M. et al. Learning heuristics for basic block instruction scheduling. J Heuristics 14, 549–569 (2008). https://doi.org/10.1007/s10732-007-9051-1

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  • DOI: https://doi.org/10.1007/s10732-007-9051-1

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