Abstract
The problems of error simulation, error model evaluation, and test generation are faced considering the peculiar features of SystemC. In particular, error simulation are considered in the perspective of the transaction level modelling (TLM) capabilities of this emerging system level design language to obtain a coherent, environment for functional verification. The error simulation is accomplished without any modification of the native simulation engine, thus avoiding the problem of upgrading the error simulator together with the language simulation engine. Moreover, error modelling and error simulation tasks are orthogonalized in this approach. With the support of this environment, a test pattern generation algorithm for SystemC descriptions of systems made of interacting Finite State Machines (FSMs) is developed. The approach is based on the definition of the transitions, that represent ordered sets of statements executed within one clock cycle. Through different state sequence paths enumeration strategies, interesting behaviors of the system are obtained.
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References
E. Dustin, J. Rashka, and J. Paul, Automated Software Testing: Introduction, Management, and Performance, Addison Wesley (1999)
R. Vemuri R. Kalyanaraman (1995) ArticleTitleGeneration of Design Verification Tests from Behavioral VHDL Programs Using Path Enumeration and Constraint Programming IEEE Trans. Very Large Scale Integration (VLSI) Systems 3 IssueID2 201–214
S. Devadas, A. Ghosh, and K. Keutzer, An Observability-Based Code Coverage Metric for Functional Simulation, in Proc Internation Conference on Computer-Aided Design (1999)
F. Ferrandi F. Fummi G. Pravadelli D. Sciuto (2003) ArticleTitleIdentification of Design Errors Through Functional Testing IEEE Trans. Reliability 52 400–412
K. Cheng A. Krishnakumar (1996) ArticleTitleAutomatic generation of functional vectors using the extended finite state machine model ACM Trans. Design Automation Electronic Sys. 1 IssueID1 57–79
S. Chiusano, F. Corno, and P. Prinetto, RT-level TPG Exploiting High-level Synthesis Information, in Proc. 17th IEEE VSLI Test Symposium (1999)
F. Ferrandi, A. Fin, F. Fummi, and D. Sciuto, An application of genetic algorithms and BDDs to functional testing, in Proc International Conference on Computer Design (2000)
M. Ganai, A. Aziz, and A. Kuehlmann, Enhancing Simulation with BDDs and ATPG, in Proc. 36th Design Automation Conference (1999)
F. Ferrandi, F. Fummi, and D. Sciuto, Implicit Test Generation for Behavioral VHDL Models, in Proc. IEEE International Test Conference (1998)
I. Ghosh M. Fujita (2001) ArticleTitleAutomatic Test Pattern Generation for Functional Register-Transfer Level Circuits using Assignment Decision Diagrams IEEE Trans. Comput. Aided Design Integrated Circuits Sys. 20 IssueID3 402–415
F. Fallah, P. Ashar, and S. Devadas, Simulation Vector Generation from HDL Descriptions for Observability-enhanced Statement Coverage, in Proc. 35th Design Automation Conference (1999)
S. Ghosh T.J. Chakraborty (1991) ArticleTitleOn Behavior Fault Modeling for Digital Designs J. Electronic Testing: Theory and Applications. 2 135–151 Occurrence Handle10.1007/BF00133499
E. Jenn, J. Arlat, M. Rimn, J. Ohisson, and J. Karlsson, Fault Injection into VHDL Models: the MEFISTO Tool, Digest of Papers of 24th International Symposium on Fault-Tolerant Computing, pp. 66–75 (1994)
J. Boue, P. Petillon, and Y. Crouzet, MEFISTO-L: A VHDL-Based Fault Injection Tool for the Experimental Assessment of Fault Tolerance, in Proc. 28th Internatiol Symposium on Fault-Tolerant Computing, pp. 168–173 (1998)
A. Ghosh, B. Johnson, and J. P. III, Performing Fault Simulation in Large System Design, in Proc. Annual Reliability and Maintainability Symposium, pp. 200–207 (1997)
B. Parrotta, M. Rebaudengo, M. S. Reorda, and M. Violante, New Techniques for Accelerating Fault Injection in VHDL Descriptions, IOLTW2000: International On-Line Test Workshop, pp. 61–66 (2000)
A. Fin, F. Fummi, and G. Pravadelli, AMLETO: A Multi-Language Environment for Functional Test Generation, in Proc. IEEE International Test Conference, pp. 821–829 (2001)
A. Fin and F. Fummi, Genetic Algorithms: The Philosopher’s Stone or an Effective Solution for High-level TPG? High-Level Design Validation and Test Workshop, 2003. Eighth IEEE International, pp. 163–168 (2003)
F. Ferrandi, F. Fummi, and D. Sciuto, Implicit test generation for behavioral VHDL models, in Proc. International Test Conference, pp. 587–596 (1998)
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Bruschi, F., Ferrandi, F. & Sciuto, D. A Framework for the Functional Verification of SystemC Models. Int J Parallel Prog 33, 667–695 (2005). https://doi.org/10.1007/s10766-005-8908-x
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DOI: https://doi.org/10.1007/s10766-005-8908-x