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Scalability and Parallel Execution of Warp Processing: Dynamic Hardware/Software Partitioning

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Abstract

Warp processors are a novel architecture capable of autonomously optimizing an executing application by dynamically re-implementing critical kernels within the software as custom hardware circuits in an on-chip FPGA. Previous research on warp processing focused on low-power embedded systems, incorporating a low-end ARM processor as the main software execution resource. We provide a thorough analysis of the scalability of warp processing by evaluating several possible warp processor implementations, from low-power to high-performance, and by evaluating the potential for parallel execution of the partitioned software and hardware. We further demonstrate that even considering a high-performance 1 GHz embedded processor, warp processing provides the equivalent performance of a 2.4 GHz processor. By further enabling parallel execution between the processes and FPGA, the parallel warp processor execution provides the equivalent performance of a 3.2 GHz processor.

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  1. Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ, 857821, USA

    Roman Lysecky

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  1. Roman Lysecky
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Correspondence to Roman Lysecky.

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Lysecky, R. Scalability and Parallel Execution of Warp Processing: Dynamic Hardware/Software Partitioning. Int J Parallel Prog 36, 478–492 (2008). https://doi.org/10.1007/s10766-008-0079-0

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  • DOI: https://doi.org/10.1007/s10766-008-0079-0

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