Abstract
Multi-core System-on-Chips (SoCs) with on-chip networks are becoming a reality after almost a decade of research. One challenge in developing such SoCs is the need of efficient and accurate simulators for design space exploration. This paper addresses this need by presenting SoCExplore, a framework for fast communication-centric design space exploration of complex SoCs with network-based interconnects. Efficiency is achieved through abstraction of computation as a high-level trace, while accuracy is maintained through cycle-accurate interconnect simulation. The flexibility offered allows for fast partition/mapping and interconnect design space exploration. In a case study, a speed-up of 94% over architectural simulation is obtained for the MPEG application. A critical evaluation of the capabilities of our (or any trace based) framework is also provided.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Intel Tera-Scale Computing: http://www.intel.com/technology/techresearch/terascale/
Intel 80 core prototype: http://www.intel.com/pressroom/archive/ releases/20060926corp.htm
Borkar, S.: Electronics beyond nano-scale CMOS. DAC (2006)
Benini, L., De Micheli, G.: Networks on chip: a new SOC paradigm. IEEE Comput. 70–78 (2002)
Dally, W.J., Towles, B.: Route packets not wires: on-chip interconnection networks. DAC (2001)
Karim, F., Nyugen, A., Dey, S.: An interconnect architecture for networking systems on chips. IEEE Micro (2002)
Wang, H.S., Zhu, X., Peh, L.S., Malik, S.: Orion: a power-performance simulator for interconnection networks. MICRO 35, Nov. 2002
Kogel, T., et al.: A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS, pp. 7–12 (2003)
Xi, J., Zhong, P.: A system-level network-on-chip simulation framework integrated with low-Level analytical models. ICCD (2006)
Brinkmann, A., et al.: On-chip interconnects for next generation system-on-chips. In: 15th Annual IEEE International ASIC/SOC Conference (2002)
Pestana, S., Rijkema, E., et al.: Cost-performance trade-offs in networks on chip: a simulation-based approach. DATE (2004)
Lu, Z., Thid, R., Millberg, M., Nilsson, E., Jantsch, A.: NNSE: nostrum network-on-chip simulation environment. In: Swedish System on Chip Conf. (2005)
Scherrer, A., Fraboulet, A., Risset, T.: Automatic phase detection for stochastic on-chip traffic generation. CODES (2006)
Tedesco, L., Mello, A., Giacomet, L., Calazans, N., Moraes, F.: Application driven traffic modeling for NoCs. SBCCI (2006)
Lahiri, K., Raghunathan, A., Dey, S.: System-level performance analysis for on-chip communication architectures. TCAD (2001)
Dumitrascu, F., Bacivarov, I., Pieralisi, L., Bonaciu, M., Jerraya, A.A.: Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. DATE (2006)
Kim, S., Im, C., Ha, S.: Schedule-aware performance estimation pf communication architecture for efficient design space exploration. CODES+ISSS (2003)
Genko, N., Micheli, G.D., et al.: A complete network-On-chip emulation framework. DATE (2005)
Zivkovic, V.D., et al.: Fast and accurate multiprocessor architecture exploration with symbolic programs. DATE (2003)
Palermo, G., Silvano, C.: PIRATE: a framework for power/performance exploration of network- on-chip architectures. PATMOS (2004)
Ching, D., Schaumont, P., Verbauwhede, I.: Integrated modeling and generation of a reconfigurable network-on-chip. In: IPDPS Workshop, p. 139 (2004)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Kalla, P., Hu, X.S. & Henkel, J. A Flexible Framework for Communication Evaluation in SoC Design. Int J Parallel Prog 36, 457–477 (2008). https://doi.org/10.1007/s10766-008-0081-6
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10766-008-0081-6