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Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis

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Abstract

Efficient utilization of the inherent parallelism of multi-core architectures is a grand challenge in the field of electronic design automation (EDA). One EDA algorithm associated with a high computational cost is automatic test pattern generation (ATPG). We present the ATPG tool TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models. We demonstrate how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches.

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References

  1. Abramovici M., Breuer M.A., Friedman A.D.: Digital Systems Testing and Testable Design. Computer Science Press, New York (1990)

    Google Scholar 

  2. Aitken, R.C.: New defect behavior at 130 nm and beyond. In: European Test Symposium, pp. 279–284 (2004)

  3. Ayari B., Kaminska B.: A new dynamic test vector compaction for automatic test pattern generation. IEEE Trans. CAD 13(3), 353–358 (1994)

    Google Scholar 

  4. Brglez, F., Bryan, D., Kozminski, K.: Combinational profiles of sequential benchmark circuits. In: International Symposium on Circuits and Systems, pp. 1929–1934 (1989)

  5. Brglez, F., Fujiwara, H.: A neutral netlist of 10 combinational circuits and a target translator in fortran. In: International Symposium on Circuits and Systems, Special Sess. on ATPG and Fault Simulation, pp. 663–698 (1985)

  6. Cho, K.Y., Mitra, S., McCluskey, E.J.: Gate exhaustive testing. In: International Test Conference (2005)

  7. Corno F., Sonza Reorda M., Squillero G.: RT-level ITC 99 benchmarks and first ATPG results. IEEE Des. Test Comput. 17(3), 44–53 (2000)

    Article  Google Scholar 

  8. Davis M., Putnam H.: A computing procedure for quantification theory. J. ACM 7(3), 201–215 (1960)

    Article  MATH  MathSciNet  Google Scholar 

  9. Desineni, R., Dwarkanath, K.N., Blanton, R.D.: Universal test generation using fault tuples. In: International Test Conference, pp. 812–819 (2000)

  10. Drechsler R., Eggersglüß S., Fey G., Glowatz A., Hapke F., Schlöffel J., Tille D.: On acceleration of SAT-based ATPG for industrial designs. IEEE Trans. CAD 27(7), 1329–1333 (2008)

    Google Scholar 

  11. Eggersglüß, S., Drechsler, R.: Improving test pattern compactness in SAT-based ATPG. In: Asian Test Symposium, pp. 445–452 (2007)

  12. El-Maleh A.H., Al-Utaibi K.: An efficient test relaxation technique for synchronous sequential circuits. IEEE Trans. CAD 23(6), 933–940 (2004)

    Google Scholar 

  13. Engelke, P., Braitling, B., Polian, I., Renovell, M., Becker, B.: SUPERB: simulator utilizing parallel evaluation of resistive bridges. In: Asian Test Symposium, pp. 433–438 (2007)

  14. Engelke P., Polian I., Renovell M., Becker B.L: Automatic test pattern generation for resistive bridging faults. J. Electron. Test. Theory Appl. 22(1), 61–69 (2006)

    Article  Google Scholar 

  15. Engelke P., Polian I., Renovell M., Becker B.: Simulating resistive bridging and stuck-at faults. IEEE Trans. CAD 25(10), 2181–2192 (2006)

    Google Scholar 

  16. Fey, G., Warode, T., Drechsler, R.: Reusing learned information in SAT-based ATPG. In: VLSI Design, IEEE Computer Society, pp. 69–76 (2007)

  17. Fujiwara, H.: FAN: A fanout-oriented test pattern generation algorithm. In: IEEE International Symposium on Circuits and Systems, pp. 671–674 (1985)

  18. Fujiwara H., Inoue T.: Optimal granularity of test generation in a distributed system. IEEE Trans. CAD 9(8), 885–892 (1990)

    Google Scholar 

  19. Gizdarski E., Fujiwara H.: SPIRIT: a highly robust combinational test generation algorithm. IEEE Trans. CAD 21(12), 1446–1458 (2002)

    Google Scholar 

  20. Goel P.: An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Trans. CAD 30, 215–222 (1981)

    Article  MATH  Google Scholar 

  21. Hamzaoglu I., Patel J.H.: New techniques for deterministic test pattern generation. J. Electron. Test. Theory Appl. 15, 63–73 (1999)

    Article  Google Scholar 

  22. Hamzaoglu I., Patel J.H.: Test set compaction algorithms for combinational circuits. IEEE Trans. CAD 19(8), 957–963 (2000)

    Google Scholar 

  23. Hillebrecht, S., Polian, I., Engelke, P., Becker, B., Keim, M., Cheng, W.-T.: Extraction, simulation and test generation for interconnect open defects based on enhanced aggressor-victim model. In: Internatinal Test Conference, pp 1–10 (2008)

  24. Kajihara, S., Miyase, K.: On identifying don’t care inputs of test patterns for combinational circuits. In: Internatinal Conference on CAD, pp. 364–369 (2001)

  25. Kajihara S., Pomeranz I., Kinoshita K., Reddy S.M.: Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. IEEE Trans. CAD 14(12), 1496–1504 (1995)

    Google Scholar 

  26. Kropf T.: Introduction to Formal Hardware Verification. Springer, Berlin (2000)

    Google Scholar 

  27. Kundu S., Zachariah S.T., Chang Y.-S., Tirumurti C.: On modeling crosstalk faults. IEEE Trans. CAD 24(12), 1909–1915 (2005)

    Google Scholar 

  28. Larrabee, T.:. Efficient generation of test patterns using Boolean difference. In: Internatinal Test Conference, pp. 795–801 (1989)

  29. Lewis, M., Schubert, T., Becker, B.: Multithreaded SAT solving. In: ASPDAC 2007, Yokohama, Japan, January 2007. 12th Asia and South Pacific Design Automation Conference (2007)

  30. Polian I., Czutro A., Kundu S., Becker B.: Power droop testing. IEEE Des. Test Comput. 24(3), 276–284 (2007)

    Article  Google Scholar 

  31. Pomeranz, I., Reddy, L.N., Reddy, S.M.: COMPACTEST: a method to generate compact test sets for combinational circuits. In: Internatinal Test Conference, pp. 194–203 (1991)

  32. Rajski J., Tyszer J., Kassab M., Mukherjee N.: Embedded deterministic test. IEEE Trans. CAD 23(5), 776–792 (2004)

    Google Scholar 

  33. Renovell M., Azaïs F., Bertrand Y.: Detection of defects using fault model oriented test sequences. J. Electron. Test. Theory Appl. 14, 13–22 (1999)

    Article  Google Scholar 

  34. Roth J.P.: Diagnosis of automata failures: a calculus and a method. IBM J. Res. Dev. 10, 278–281 (1966)

    Article  MATH  Google Scholar 

  35. Rudnick E.M., Patel J.H.: Efficient techniques for dynamic test sequence compaction. IEEE Trans. Comput. 48(3), 323–330 (1999)

    Article  Google Scholar 

  36. Sar-Dessai, V., Walker, D.M.H.: Resistive bridge fault modeling, simulation and test generation. In: Internatinal Test Conference, pp. 596–605 (1999)

  37. Sato, Y., Yamazaki, I., Yamanaka, H., Ikeda, T., Takakura, M.: A persistent diagnostic technique for unstable defects. In: Internatinal Test Conference, pp. 242–249 (2002)

  38. Schubert T., Lewis M., Becker B.: PaMiraXT: Parallel SAT solving with threads and message passing. J. Satisfiability, Boolean Model. Comput. 6, 203–222 (2009)

    MATH  Google Scholar 

  39. Shinogi, T., Kanbayashi, T., Yoshikawa, T., Tsuruoka, S., Hayashi, T.: Faulty resistance sectioning technique for resistive bridging fault ATPG systems. In: Asian Test Symposium, pp. 76–81 (2001)

  40. Siewiorek D.P., Swarz R.S.: Reliable Computer Systems—Design and Evaluation. Digital Press, Belford (1992)

    Google Scholar 

  41. Smith, G.L.: Model for delay faults based upon paths. In: International Test Conference, pp. 342–349 (1985)

  42. Snir M., Otto S.W., Walker D.W., Dongarra J., Huss-Lederman S.: MPI: The Complete Reference. MIT Press, Cambridge (1996)

    Google Scholar 

  43. Stephan P., Brayton R., Sangiovanni-Vincentelli A.: Combinational test generation using satisfiability. IEEE Trans. CAD 15(9), 1167–1176 (1996)

    Google Scholar 

  44. Tafertshofer, P., Ganz, A.: SAT based ATPG using fast justification and propagation in the implication graph. In: Internatinal Conference on CAD, pp.139–146 (1999)

  45. Wang, C., Reddy, S.M., Pomeranz, I., Lin, X., Rajski, J.: Conflict driven techniques for improving deterministic test pattern generation. In: Internatinal Conference on CAD (2002)

  46. Zhang M., Mitra S., Mak T.M., Seifert N., Wang N.J., Shi Q., Kim K.S., Shanbhag N.R., Patel S.J.: Sequential element design with built-in soft error resilience. IEEE Trans. VLSI Syst. 14(12), 1368–1378 (2006)

    Article  Google Scholar 

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Authors and Affiliations

  1. Computer Architecture Group, Institute for Computer Science, Albert-Ludwigs-University, Georges-Köhler-Allee 51, 79110, Freiburg i. Br., Germany

    Alexander Czutro, Ilia Polian, Matthew Lewis, Piet Engelke & Bernd Becker

  2. ECE Department, University of Iowa, Iowa City, IA, 52242, USA

    Sudhakar M. Reddy

Authors
  1. Alexander Czutro
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  2. Ilia Polian
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  3. Matthew Lewis
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  4. Piet Engelke
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  5. Sudhakar M. Reddy
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  6. Bernd Becker
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Correspondence to Ilia Polian.

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Czutro, A., Polian, I., Lewis, M. et al. Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Int J Parallel Prog 38, 185–202 (2010). https://doi.org/10.1007/s10766-009-0124-7

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  • DOI: https://doi.org/10.1007/s10766-009-0124-7

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