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Bandwidth Adaptive Cache Coherence Optimizations for Chip Multiprocessors

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Abstract

Chip Multiprocessors (CMPs) have different technological parameters and physical constraints than earlier multi-processor systems, which should be taken into consideration when designing cache coherence protocols. Also, contemporary cache coherence protocols use invalidate schemes that are known to generate a high number of coherence misses. This is especially true under producer-consumer sharing patterns that can become a performance bottleneck as the number of cores increases. This paper presents two mechanisms to design efficient and scalable cache coherence protocols for CMPs. First, we propose an adaptive hybrid protocol to reduce coherence misses observed in write-invalidate based protocols. The proposed protocol is based on a write-invalidate scheme. However, adaptively, it can push updates to potential consumers based on observed producer-consumer sharing patterns. Secondly, we extend this adaptive protocol with an interconnection resource aware mechanism. Experimental evaluations, conducted on a tiled-CMP via full-system simulation, were used to assess the performance from our proposed dynamic hybrid protocols. Performance analysis is presented on a set of scientific applications from the SPLASH-2 and NAS parallel benchmark suites. Results showed that the proposed mechanisms reduce cache-to-cache sharing misses up to 48 % and speed up application performance up to 34 %. In addition, the proposed interconnection resource aware mechanism is proven to perform well under varying interconnection utilizations.

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Acknowledgments

Authors would like to thank Dan Gibson from Google, formerly at University of Wisconsin Multifacet group, for his help and suggestions on our implementations in GEMS simulation infrastructure. Authors also would like to thank Arctic Region Supercomputing Center (ARSC) for their support in this research.

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Authors and Affiliations

  1. Intel PTD, Hillsboro, OR, USA

    Abdullah Kayi

  2. The George Washington University, Washington, DC, USA

    Olivier Serres & Tarek El-Ghazawi

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  1. Abdullah Kayi
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  2. Olivier Serres
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  3. Tarek El-Ghazawi
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Correspondence to Abdullah Kayi.

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Kayi, A., Serres, O. & El-Ghazawi, T. Bandwidth Adaptive Cache Coherence Optimizations for Chip Multiprocessors. Int J Parallel Prog 42, 435–455 (2014). https://doi.org/10.1007/s10766-013-0247-8

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