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Power Efficiency for Hardware/Software Partitioning with Time and Area Constraints on MPSoC

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Abstract

Hardware/software partitioning is a crucial step in hardware/software co-design for energy-efficient, high-performance systems. Previous research efforts mainly focused on single processor architecture. Their methods can not produce high-quality solutions to the problem of hardware/software partitioning for multiprocessor systems. In this paper, we propose two algorithms for hardware/software partitioning problem on MPSoC, to minimize power consumption with time and area constraints. The Tree_Partitioning algorithm generates optimal partitioning results for tree-structured control-flow graphs using dynamic programming. For the general partitioning problem, we propose the DAG_Partitioning algorithm to produce near optimal solution efficiently for directed-acyclic graphs. The experimental results show that our proposed algorithms outperform existing techniques for a set of benchmarks with various time and area constraints.

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Acknowledgments

This work is partially supported by NSF CNS-1015802, Texas NHARP 009741-0020-2009, NSFC 61173014, National 863 Program 2013AA013202, Chongqing cstc2012ggC40005.

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Authors and Affiliations

  1. College of Computer Science, Chongqing University, Chongqing, 400044, China

    Edwin Sha, Qingfeng Zhuge & Jun Zhang

  2. Department of Computer Science, University of Texas at Dallas, Richardson, TX, 75080, USA

    Edwin Sha

  3. College of Information Science and Engineering, Hunan University, Changsha, 410082, China

    Li Wang & Jing Liu

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  1. Edwin Sha
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  2. Li Wang
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  3. Qingfeng Zhuge
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  4. Jun Zhang
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Correspondence to Qingfeng Zhuge.

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Sha, E., Wang, L., Zhuge, Q. et al. Power Efficiency for Hardware/Software Partitioning with Time and Area Constraints on MPSoC. Int J Parallel Prog 43, 381–402 (2015). https://doi.org/10.1007/s10766-013-0283-4

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  • DOI: https://doi.org/10.1007/s10766-013-0283-4

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