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High Performance GCM Architecture for the Security of High Speed Network

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Abstract

Advanced Encryption Standard (AES) is an effective cryptography algorithm for providing the better data communication since it guaranties high security. The Galois/Counter Mode (AES-GCM) has been integrated in various security constrained applications because it provides both authentication and confidentiality. AES algorithm helps to provide data confidentiality while authentication is provided by a universal GHASH function. Since most of existing GCM architectures concentrated on power and area reduction but an compact and efficient hardware architecture should also be considered. In this paper, high-performance architecture for GCM is proposed and its implementation is described. In order to achieve higher operating frequency and throughput, pipelined S-boxes are used in AES algorithm. For a GCM realization of AES, a high-speed, high-throughput, parallel architecture is proposed. Experimental results proves that the performance of the proposed work is around 17% higher than the existing architecture with 3 Gb/s throughput using TSMC 45-nm CMOS technology.

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References

  1. Cuomo, S., Michele, P.D., Piccialli, F., Galletti, A., Jung, J.E.: IoT-based collaborative reputation system for associating visitors and artworks in a cultural scenario. Expert Syst. Appl. 79, 101–111 (2017)

    Article  Google Scholar 

  2. Chianese, A., Marulli, F., Moscato, V., Piccialli, F.: A smart multimedia guide for indoor contextual navigation in Cultural Heritage applications. In: Proceedings of International Conference on Indoor Positioning and Indoor Navigation, IPIN 2013, (2013)

  3. Chianese, A., Piccialli, F.: SmaCH: a framework for smart cultural heritage spaces. In: Proceedings of 10th International Conference on Signal-Image Technology and Internet-Based Systems, SITIS 2014, pp. 477–484 (2015)

  4. Vliegen, J., Reparaz, O., Mentens, N.: Maximizing the throughput of threshold-protected AES-GCM implementations on FPGA. In: 2017 IEEE 2nd International Verification and Security Workshop (IVSW), pp. 140–145. IEEE (2017)

  5. Paul, A., Victoire, T.A.A., Jeyakumar, A.E.: Partical swarm approach for retiming in VLSI. In: 2003 46th Midwest Symposium on Circuits and Systems, vol. 3, pp. 1532–1535 (2003)

  6. Koteshwara, S., Das, A., Parhi, K.K.: FPGA implementation and comparison of AES-GCM and Deoxys authenticated encryption schemes. In: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–4. IEEE (2017)

  7. Satoh, A., Sugawara, T., Aoki, T.: High-performance hardware architectures for galois counter mode. IEEE Trans. Comput. 58(7), 917–930 (2009)

    Article  MathSciNet  Google Scholar 

  8. Farina, R., Cuomo, S., De Michele, P., Piccialli, F.: A smart GPU implementation of an elliptic kernel for an ocean global circulation model. Appl. Math. Sci. 7(61–64), 3007–3021 (2013)

    Google Scholar 

  9. An, T., de Barros Naviner, L.A., Matherat, P.: A low cost reliable architecture for S-boxes in AES processors. In: Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), New York, pp. 155–160, USA (2013)

  10. Kumar, Saurabh, Sharma, V.K., Mahapatra, K.K.: An improved VLSI architecture of S-box for AES encryption. Proceedings of International Conference on Communication Systems and Network Technologies, Gwalior, pp. 753–756, India (2013)

  11. Abhiram, L.S., Sriroop, B.K., Gowrav, L., Punith, K.H., Lakkannavar, M.C.: FPGA implementation of dual key based AES encryption with key based S-box generation. In: Proceedings of International Conference on Computing for Sustainable Global Development (INDIACom), New Delhi, pp. 577–581, India (2015)

  12. Kasper, E., Schwabe, P.: Faster and timing-attack resistant AES-GCM. In: Proceedings of International Workshop Cryptographic Hardware and Embedded Systems (CHES ’09), Lausanne, pp. 1–17, Switzerland (2009)

  13. McGrew, D.A., Viega, J.: The Galois/Counter Mode of Operation (GCM), NIST Modes Operation Symmetric Key Block Ciphers (2005)

  14. Meloni, N., Negre, C., Hasan, M.A.: High performance GHASH function for long messages. In: Proceedings of International Conference on Applied Cryptography and Network Security (ACNS ’10), Beijing, pp. 154–167, China (2010)

  15. Kumar, S., Sharma, V.K., Mahapatra, K.K.: Low latency VLSI architecture of S-box for AES encryption. In: Proceedings of International Conference on Circuits, Power and Computing Technologies (ICCPCT), Nagercoil, pp. 694–698, India (2013)

  16. Elliptic Semiconductor Inc.: Ultra-high throughput AESGCMCore-40 Gbps (2008)

  17. Wu, H.: On computation of polynomial modular reduction. Technical Report Center for Applied and Cryptographic Research (2000)

  18. Helion Technology.: AES-GCM Cores (2007)

  19. National Institute of Standards and Technologies: Announcing the Advanced Encryption Standard (AES), Information Processing Standards Publication. No. 197, pp. 1–51 (2001)

  20. Vanitha, M., Sakthivel, R., Subha, S.: Highly secured high throughput VLSI architecture for AES algorithm. In:International Conference on Devices, Circuits and Systems(ICDCS), Coimbatore, pp. 403–407, India (2012)

  21. Paul, A., Ahmad, A., Rathore, M., Jabbar, S.: Smartbuddy: defining human behaviors using big data analytics in social internet of things. IEEE Wirel. Commun. 23(5), 68–74 (2016)

    Article  Google Scholar 

  22. Paul, A., Daniel, A., Ahmad, A., Rho, S.: Cooperative cognitive intelligence for internet of vehicles. IEEE Syst. J. 11(3), 1249–1258 (2015)

    Article  Google Scholar 

  23. Paul, A.: Real-time power management for embedded M2M using intelligent learning methods. ACM Trans. Embed. Comput. Syst. (TECS) 13(5s), 148 (2014)

    Google Scholar 

  24. Satoh, A., Morioka, S., Takano, K., Munetoh, S.: A compact Rijndael hardware architecture with S-box optimization. In: International Conference on the Theory and Application of Cryptology and Information Security ASIACRYPT, Gold Coast, pp. 239–254, Australia (2001)

  25. Zhou, G., Michalik, H., Hinsenkamp, L.: Efficient and high-throughput implementations of AES-GCM on FPGAs. In: Proceedings of International Conference on Field-Programmable Technology (ICFPT), Kitakyushu, pp. 185–192, Japan (2007)

  26. Yang, B., Mishra, S., Karri, R.: High speed architecture for Galois/counter mode of operation (GCM). In: International Association for Cryptologic Research (IACR), pp. 47–50 (2005)

  27. Hodjat, A., Verbauwhede, I.: Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors. IEEE Trans. Comput. 55(4), 366–372 (2006)

    Article  Google Scholar 

  28. Bellare, M., Rogaway, P., Wagner, D.: The EAX mode of operation. In: Proceedings of Fast Software Encryption(FSE), Delhi, pp. 389–407, India (2004)

  29. Mozaffari Kermani, M., Reyhani-Masoleh, A.: Efficient and high-performance parallel hardware architectures for the AES-GCM. IEEE Trans. Comput. 61(8), 1165–1178 (2012)

    Article  MathSciNet  Google Scholar 

  30. Piccialli, F., Cuomo, S., De Michele, P.: A regularized MRI image reconstruction based on hessian penalty term on CPU/GPU systems. Procedia Comput. Sci. 18, 2643–2646 (2013)

    Article  Google Scholar 

  31. Parhi, K.K.: VLSI Digital Signal Processing Systems: Design and Implementation, Chap. 3. Wiley, Hoboken (1999)

  32. Satoh, A.: High-speed parallel hardware architecture for Galois counter mode. In: International Symposium on Circuits and Systems (ISCAS), pp. 1863–1866, New Orleans, Los Angeles (2007)

  33. Ali, S.S., Sinanoglu, O., Karri, R.: AES design space exploration new line for scan attack resiliency. In: Proceedings of IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Playa del Carmen, pp. 1–6, Mexico (2014)

  34. Ege, B., Das, A., Gosh, S., Verbauwhede, I.: Differential scan attack on AES with X-tolerant and X-masked test response compactor. In: Proceedings of Euromicro Conference on Digital System Design, Izmir, pp. 545–552, Turkey (2012)

  35. DaRolt, J., Natale, G.D., Flottes, M.L., Rouzeyre, B.: Scan attacks and countermeasures in presence of scan response compactors. In: Proceedings of European Test Symposium (ETS), Trondheim, pp. 19–24, Norway (2011)

  36. Mitra, S., Mitzenmacher, M., Lumetta, S.S., Patil, N.: X-tolerant test response compaction. Des. Test Comput. 22(6), 566–574 (2005)

    Article  Google Scholar 

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Acknowledgements

This study was supported by the Next-Generation Information Computing Development Program through National Research Foundation of Korea (NRF) grant funded by the Korean Government (MSIT) (2017M3C4A7066010). This study was also supported by the National Research Foundation of Korea (NRF) grant funded by the Korean Government (NRF-2017R1C1B5017464).

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Authors and Affiliations

  1. Vellore Institute of Technology, Vellore, India

    Vanitha Mohanraj & R. Sakthivel

  2. The School of Computer Science and Engineering, Kyungpook National University, Daegu, South Korea

    Anand Paul

  3. Department of Media Software, Sungkyul University, Anyang, South Korea

    Seungmin Rho

Authors
  1. Vanitha Mohanraj
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  2. R. Sakthivel
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  3. Anand Paul
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  4. Seungmin Rho
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Correspondence to Anand Paul.

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Mohanraj, V., Sakthivel, R., Paul, A. et al. High Performance GCM Architecture for the Security of High Speed Network. Int J Parallel Prog 46, 904–922 (2018). https://doi.org/10.1007/s10766-017-0545-7

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  • DOI: https://doi.org/10.1007/s10766-017-0545-7

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