Abstract
Adaptive routing algorithms can improve performance by balancing load across network channels in the presence of non-uniform traffic patterns. However, out-of-order packets can be introduced due to multi-path transmission of adaptive routing. With out-of-order transmission in the network, packets need to be reordered at the destination before being absorbed. Increasing network size with adaptive routing makes the time when a packet arrives at the destination extremely uncertain, which requires a large buffer to reorder the packets and this can exceed design space. Therefore, the challenge is to balance the trade-off between multi-path transmission and packet reordering. In this paper, we propose a novel packet reordering metric-OOD to quantify the degree of out-of-order. To minimize the OOD of packets, we propose DancerFly, an order-aware network-on-chip router that mitigates out-of-order packets caused by adaptive routing. DancerFly achieves this goal by providing two-level reordering. First, it performs in-buffer reordering by reordering packets queuing in the input buffer. Second, packets from different input ports are reordered before traversing through the router. We evaluate our design and the results show that the OOD can be reduced by 36.3% with comparable performance to the baseline.
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Notes
A set of paths are defined to be non-intersecting if the paths originate from the same source vertex but do not intersect each other in the network, except at the destination vertex.
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Acknowledgements
We thank the anonymous reviewers for their valuable feedback. We also appreciate members of Tianhe interconnect group at NUDT for many inspiring conversations early in the project. This project was partially supported by the National Science and Technology Major Projects on Core Electronic Devices, High-End Generic Chips and Basic Software under grants No.2018ZX01028101 and No. 2017ZX01038104-002.
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Jin, K., Dong, D., Li, C. et al. DancerFly: An Order-Aware Network-on-Chip Router On-the-Fly Mitigating Multi-path Packet Reordering. Int J Parallel Prog 48, 730–749 (2020). https://doi.org/10.1007/s10766-019-00648-9
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DOI: https://doi.org/10.1007/s10766-019-00648-9