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A Timed-Value Stream Based ESL Timing and Power Estimation and Simulation Framework for Heterogeneous MPSoCs

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Abstract

Consideration of an embedded system’s timing behavior and power consumption at system-level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard- and software as well as IP components. In this article we present an ESL framework for timing and power aware virtual system prototyping of heterogeneous MPSoCs consisting of software, custom hardware and 3rd party IP components. In virtual platform, previously only used for functional software verification, our proposed timed value streams enable a hierarchical and composable power model. Our proposed ESL framework supports the integration of a broad range of system-level timing and power models into virtual platform. Power and timing models can either be generated from a functional C/C++ description or include state-machine based power models to existing functional and timed virtual platform (black-box) components. Our timed value stream based power model supports the run-time analysis of different platform power management strategies with configurable temporal abstraction, supporting simulation speed and accuracy trade-offs. This work evaluates timing and power back-annotation and power state machine based approaches with timed value streams in two use-cases: An MP3 decoder, compared to a power-aware ISS and gate-level simulation, and an FPGA based many-core architecture against measurements. Finally, the simulation time overhead of the proposed stream based power model is analyzed and discussed.

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Notes

  1. Sometimes also called non-functional properties. In this work extra-functional properties specify all metrics beyond the behavior. Here we focus on the extra-functional properties timing and power consumption. More details can be found in Sect. 3.3.

  2. We sometimes omit j for improved readability.

  3. This classification is loosely adopted from the theory of thermodynamics. Sometimes, these classes are called state and process functions.

  4. The starting time is assumed to be aligned already.

  5. We do not consider the temperature dependent leakage power here, for this reason the measurement has been stared after a warm-up phase with stable temperature of the system.

  6. Since the “no stream processor” scenario only generates power values without containing any functional behavior.

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Acknowledgements

This work has been partially supported by the EU Integrated Projects COMPLEX (FP7-247999) and CONTREX (FP7-611146), by the BMBF Projects SANITAS (01M3088C) and RESCAR 2.0 (01M3195E).

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Authors and Affiliations

  1. OFFIS - Institute for Information Technology, Eschwerweg 2, 26121, Oldenburg, Germany

    Kim Grüttner, Philipp A. Hartmann, Tiemo Fandrey, Kai Hylla, Daniel Lorenz & Wolfgang Nebel

  2. ABB Corporate Research, Wallstadter Straße 59, 68526, Ladenburg, Germany

    Stefan Hauck-Stattelmann

  3. Hitex Development Tools GmbH, Greschbachstr. 12, 76229, Karlsruhe, Germany

    Björn Sander

  4. Universität Tübingen, Sand 13, 72076, Tübingen, Germany

    Oliver Bringmann & Wolfgang Rosenstiel

  5. Carl von Ossietzky Universität Oldenburg, Ammerländer Heerstr. 114-118, 26111, Oldenburg, Germany

    Wolfgang Nebel

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  1. Kim Grüttner
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Grüttner, K., Hartmann, P.A., Fandrey, T. et al. A Timed-Value Stream Based ESL Timing and Power Estimation and Simulation Framework for Heterogeneous MPSoCs. Int J Parallel Prog 48, 957–1007 (2020). https://doi.org/10.1007/s10766-020-00656-0

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