Abstract
Digital signal processing (DSP) systems are becoming popular with the emergence of artificial intelligence and machine learning based applications. Residue number system is one of most sought representation for implementing the high speed DSP systems. This paper presents an efficient implementation of memory less distributed arithmetic (MLDA) architecture in finite impulse response filter with residual number system. The input data and filter coefficients of MLDA are in residue number form and the output data from MLDA is converted into binary form using Chinese remainder theorem. In addition, compressor adders are used to reduce the area. For real time validation, the proposed design has been simulated and synthesized in application specific integrated circuit platform using synopsis design compiler with CMOS 90 nm technology. The results show that the proposed design has very high computation speed with total delay of only 20 ns and occupies 20% less area in comparison with the existing designs.
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Jyothi, G.N., Sanapala, K. & Vijayalakshmi, A. ASIC implementation of distributed arithmetic based FIR filter using RNS for high speed DSP systems. Int J Speech Technol 23, 259–264 (2020). https://doi.org/10.1007/s10772-020-09683-1
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DOI: https://doi.org/10.1007/s10772-020-09683-1