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Simulating Circuit-Level Simplifications on CNF

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Abstract

Boolean satisfiability (SAT) and its extensions have become a core technology in many application domains, such as planning and formal verification, and continue finding various new application domains today. The SAT-based approach divides into three steps: encoding, preprocessing, and search. It is often argued that by encoding arbitrary Boolean formulas in conjunctive normal form (CNF), structural properties of the original problem are not reflected in the CNF. This should result in the fact that CNF-level preprocessing and SAT solver techniques have an inherent disadvantage compared to related techniques applicable on the level of more structural SAT instance representations such as Boolean circuits. Motivated by this, various simplification techniques and intricate CNF encodings for circuit-level SAT instance representations have been proposed. On the other hand, based on the highly efficient CNF-level clause learning SAT solvers, there is also strong support for the claim that CNF is sufficient as an input format for SAT solvers. In this work we study the effect of CNF-level simplification techniques, focusing on SatElite-style variable elimination (VE) and what we call blocked clause elimination (BCE). We show that BCE is surprisingly effective both in theory and in practice on CNF formulas resulting from a standard CNF encoding for circuits: without explicit knowledge of the underlying circuit structure, it achieves the same level of simplification as a combination of circuit-level simplifications and previously suggested polarity-based CNF encodings. We also show that VE can achieve many of the same effects as BCE, but not all. On the other hand, it turns out that VE and BCE are indeed partially orthogonal techniques. We also study the practical effects of combining BCE and VE for reducing the size of formulas and on the running times of state-of-the-art SAT solvers. Furthermore, we address the problem of how to construct original witnesses to satisfiable CNF formulas when applying a combination of BCE and VE.

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Authors and Affiliations

  1. Department of Computer Science, University of Helsinki, PO Box 68, 00014, Helsinki, Finland

    Matti Järvisalo

  2. Institute for Formal Models and Verification, Johannes Kepler University, Altenbergerstr. 92, 4040, Linz, Austria

    Armin Biere

  3. Department of Software Technology, Delft University of Technology, Mekelweg 4, 2628 CD, Delft, The Netherlands

    Marijn J. H. Heule

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  1. Matti Järvisalo
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  3. Marijn J. H. Heule
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Correspondence to Matti Järvisalo.

Additional information

Parts of this article have been preliminarily presented at the 16th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS 2010) [30] and at the 13th International Conference on Theory and Applications of Satisfiability Testing (SAT 2010) [29].

The first author is financially supported by Academy of Finland under grant 132812. The second and the third author are supported by the Austrian Science Foundation (FWF) NFN Grant S11408-N23 (RiSE). The third author is supported by the Dutch Organization for Scientific Research under grant 617.023.611.

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Järvisalo, M., Biere, A. & Heule, M.J.H. Simulating Circuit-Level Simplifications on CNF. J Autom Reasoning 49, 583–619 (2012). https://doi.org/10.1007/s10817-011-9239-9

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